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* Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-083-0/+6
| | | | llvm-svn: 83526
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-082-19/+2
| | | | llvm-svn: 83522
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-082-64/+10
| | | | llvm-svn: 83521
* Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-083-0/+6
| | | | llvm-svn: 83518
* Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-083-0/+5
| | | | llvm-svn: 83513
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+6
| | | | llvm-svn: 83508
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+6
| | | | llvm-svn: 83506
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+5
| | | | llvm-svn: 83502
* reverting thumb1 scavenging default due to test failure while I figure out ↵Jim Grosbach2009-10-072-9/+64
| | | | | | what's up. llvm-svn: 83501
* Fix handling of x86 'R' constraint.Dale Johannesen2009-10-071-1/+8
| | | | llvm-svn: 83499
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-072-64/+9
| | | | llvm-svn: 83494
* Add some instruction encoding bits for NEON load/store instructions.Bob Wilson2009-10-072-140/+165
| | | | llvm-svn: 83490
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-9/+94
| | | | llvm-svn: 83486
* Add codegen support for NEON vst3 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-9/+88
| | | | llvm-svn: 83484
* Add codegen support for NEON vst2 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-7/+47
| | | | llvm-svn: 83482
* Add codegen support for NEON vld4 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-7/+83
| | | | llvm-svn: 83479
* Add another bit of the ARM target assembler to llvm-mc to parse registersKevin Enderby2009-10-071-3/+17
| | | | | | | | with writeback, things like "sp!", etc. Also added some more stuff to the temporarily hacked methods ARMAsmParser::MatchRegisterName and ARMAsmParser::MatchInstruction to allow more parser testing. llvm-svn: 83477
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-076-90/+0
| | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
* Add codegen support for NEON vld3 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-13/+92
| | | | llvm-svn: 83471
* Rearrange code for selecting vld2 intrinsics. No functionality change.Bob Wilson2009-10-071-9/+14
| | | | | | This is just to be more consistent with the forthcoming code for vld3/4. llvm-svn: 83470
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-0726-75/+123
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Add PseudoSourceValues for constpool stuff on ELF (Darwin should use ↵Anton Korobeynikov2009-10-072-12/+34
| | | | | | | | something similar) and register spills. llvm-svn: 83435
* Added bits of the ARM target assembler to llvm-mc to parse some load instructionKevin Enderby2009-10-061-1/+404
| | | | | | | operands. Some parsing of arm memory operands for preindexing and postindexing forms including with register controled shifts. This is a work in progress. llvm-svn: 83424
* Add codegen support for NEON vld2 operations on quad registers.Bob Wilson2009-10-064-1/+62
| | | | llvm-svn: 83422
* Use copyRegToReg hook to copy registers.Bob Wilson2009-10-061-6/+4
| | | | llvm-svn: 83421
* Fix a comment typo.Bob Wilson2009-10-061-1/+1
| | | | | | Patch by Johnny Chen. llvm-svn: 83407
* Instead of printing unnecessary basic block labels as labels inDan Gohman2009-10-0612-37/+4
| | | | | | | | | | verbose-asm mode, print comments instead. This eliminates a non-comment difference between verbose-asm mode and non-verbose-asm mode. Also, factor out the relevant code out of all the targets and into target-independent code. llvm-svn: 83392
* Remove xs1b predicate since it is no longer needed to differentiate betweemRichard Osborne2009-10-064-33/+5
| | | | | | xs1a and xs1b. llvm-svn: 83383
* Remove xs1a subtarget. xs1a is a preproduction device used inRichard Osborne2009-10-067-98/+45
| | | | | | | early development boards which is no longer supported in the XMOS toolchain. llvm-svn: 83381
* Default to the xs1b subtargetRichard Osborne2009-10-061-1/+1
| | | | llvm-svn: 83380
* Update processDebugLoc() so that it can be used to process debug info before ↵Devang Patel2009-10-0616-22/+39
| | | | | | and after printing an instruction. llvm-svn: 83363
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-053-3/+36
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* Remove explicit enum integer values. They don't appear to be needed, andDan Gohman2009-10-052-22/+22
| | | | | | they make it less convenient to add new entries. llvm-svn: 83308
* Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIPDan Gohman2009-10-051-5/+5
| | | | | | is used in an operand which requires GR64_NOREX. llvm-svn: 83307
* strength reduce a ton of type equality tests to check the typeid (ThroughChris Lattner2009-10-052-7/+7
| | | | | | | | the new predicates I added) instead of going through a context and doing a pointer comparison. Besides being cheaper, this allows a smart compiler to turn the if sequence into a switch. llvm-svn: 83297
* Add a comment to describe letters used in multiclass name suffixes.Bob Wilson2009-10-031-0/+6
| | | | llvm-svn: 83257
* Fix encoding problem for VMLS instruction.Bob Wilson2009-10-031-1/+1
| | | | | | Thanks to Johnny Chen for pointing this out! llvm-svn: 83256
* getFunctionAlignment should return log2 alignment.Evan Cheng2009-10-022-3/+4
| | | | llvm-svn: 83242
* Forgot about ARM::tPUSH. It also has a new writeback operand.Evan Cheng2009-10-021-0/+1
| | | | llvm-svn: 83237
* Move load / store multiple before post-alloc scheduling.Evan Cheng2009-10-021-10/+2
| | | | llvm-svn: 83236
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-012-5/+8
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-012-5/+6
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-013-2/+6
| | | | llvm-svn: 83214
* Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,Evan Cheng2009-10-015-24/+33
| | | | | | ld / st pairs, etc. llvm-svn: 83197
* Update ARM JIT emitter to account for ld/st multiple changes.Evan Cheng2009-10-011-3/+3
| | | | llvm-svn: 83192
* Change ld/st multiples to explicitly model the writeback to base register. ↵Evan Cheng2009-10-016-40/+55
| | | | | | This fixes most of the -ldstopti-before-sched2 regressions. llvm-svn: 83191
* Use MachineInstr as an processDebugLoc() argument.Devang Patel2009-09-3012-12/+12
| | | | | | This will allow processDebugLoc() to handle scopes for DWARF debug info. llvm-svn: 83183
* Use OutStreamer.SwitchSection instead of writing out textual section directives.Bob Wilson2009-09-301-7/+18
| | | | | | | Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to get access to that section. llvm-svn: 83178
* Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use thisBob Wilson2009-09-304-23/+9
| | | | | | | | | | | | | | | | to emit target-specific things at the beginning of the asm output. This fixes a problem for PPC, where the text sections are not being kept together as expected. The base class doInitialization code calls DW->BeginModule() which emits a bunch of DWARF section directives. The PPC doInitialization code then emits all the TEXT section directives, with the intention that they will be kept together. But as I understand it, the Darwin assembler treats the default TEXT section as a special case and moves it to the beginning of the file, which means that all those DWARF sections are in the middle of the text. With this change, the EmitStartOfAsmFile hook is called before the DWARF section directives are emitted, so that all the PPC text section directives come out right at the beginning of the file. llvm-svn: 83176
* Fix a comment typo.Bob Wilson2009-09-301-1/+1
| | | | llvm-svn: 83174
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