summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Remove the getAttributesAtIndex and getNumAttrs methods in favor of using ↵Bill Wendling2012-12-311-5/+2
| | | | | | the getAttrSomewhere predicate. This prevents the uses of 'Attribute' as a collection of attributes. llvm-svn: 171271
* convert a bunch of callers from DataLayout::getIndexedOffset() to ↵Nuno Lopes2012-12-301-10/+5
| | | | | | | | | GEP::accumulateConstantOffset(). The later API is nicer than the former, and is correct regarding wrap-around offsets (if anyone cares). There are a few more places left with duplicated code, which I'll remove soon. llvm-svn: 171259
* Use the predicate methods off of AttributeSet instead of Attribute.Bill Wendling2012-12-303-4/+3
| | | | llvm-svn: 171257
* Remove the Function::getRetAttributes method in favor of using the ↵Bill Wendling2012-12-302-6/+3
| | | | | | AttributeSet accessor method. llvm-svn: 171256
* Remove Function::getParamAttributes and use the AttributeSet accessor ↵Bill Wendling2012-12-301-1/+1
| | | | | | methods instead. llvm-svn: 171255
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-3013-37/+51
| | | | | | | | | directly. This is in preparation for removing the use of the 'Attribute' class as a collection of attributes. That will shift to the AttributeSet class instead. llvm-svn: 171253
* s/hasAttribute/contains/g to be more consistent with other method names.Bill Wendling2012-12-301-2/+2
| | | | llvm-svn: 171252
* Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to ↵Craig Topper2012-12-293-26/+7
| | | | | | target-independent ISD nodes and use the existing patterns for those. llvm-svn: 171237
* Merge similar functionality using a nested switch.Craig Topper2012-12-291-8/+39
| | | | llvm-svn: 171229
* Remove intrinsic specific instructions for SSE/SSE2/AVX floating point ↵Craig Topper2012-12-293-74/+29
| | | | | | max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. llvm-svn: 171227
* Simplify code, no functionality change.Jakub Staszak2012-12-291-19/+14
| | | | llvm-svn: 171226
* Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.Jakub Staszak2012-12-291-0/+0
| | | | llvm-svn: 171225
* CostModel: initial checkin for code that estimates the cost of special shuffles.Nadav Rotem2012-12-282-0/+18
| | | | llvm-svn: 171180
* wrap 80-col lines.Nadav Rotem2012-12-281-2/+5
| | | | llvm-svn: 171179
* AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these ↵Nadav Rotem2012-12-282-45/+71
| | | | | | optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. llvm-svn: 171178
* Reverse the 'if' condition and reduce the indentation.Nadav Rotem2012-12-271-29/+28
| | | | llvm-svn: 171172
* Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.Craig Topper2012-12-271-28/+28
| | | | llvm-svn: 171171
* AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a ↵Nadav Rotem2012-12-272-42/+53
| | | | | | lowering function. llvm-svn: 171170
* Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.Craig Topper2012-12-271-49/+41
| | | | llvm-svn: 171166
* On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sizedNadav Rotem2012-12-271-15/+106
| | | | | | | | | | register. In most cases we actually compare or select YMM-sized registers and mixing the two types creates horrible code. This commit optimizes some of the transition sequences. PR14657. llvm-svn: 171148
* AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom ↵Nadav Rotem2012-12-271-106/+96
| | | | | | | | | | lowering hook. The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps. No new testcase because the original testcases still work. llvm-svn: 171146
* Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.Craig Topper2012-12-271-0/+3
| | | | llvm-svn: 171143
* Move single letter 'P' prefix out of multiclass now that tablegen allows ↵Craig Topper2012-12-271-86/+85
| | | | | | defm to start with #NAME. This makes instruction names more searchable again. llvm-svn: 171141
* Add hasSideEffects=0 to some shift and rotate instructions. None of which ↵Craig Topper2012-12-271-1/+5
| | | | | | are currently used by code generation. llvm-svn: 171137
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-271-0/+2
| | | | llvm-svn: 171136
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-271-0/+1
| | | | llvm-svn: 171130
* Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC ↵Craig Topper2012-12-271-19/+43
| | | | | | instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
* Fix operands and encoding form for ARPL instruction. Register form had and ↵Craig Topper2012-12-261-2/+2
| | | | | | reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
* Add hasSideEffects=0 to some atomic instructions.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171122
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ↵Craig Topper2012-12-261-43/+44
| | | | | | side effects. llvm-svn: 171121
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-264-9/+10
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. llvm-svn: 171118
* Remove a special conditional setting of neverHasSideEffects if the ↵Craig Topper2012-12-261-4/+3
| | | | | | instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. llvm-svn: 171117
* Merge still more SSE/AVX instruction definitions.Craig Topper2012-12-261-43/+15
| | | | llvm-svn: 171103
* Merge more SSE/AVX instruction definitions.Craig Topper2012-12-261-129/+49
| | | | llvm-svn: 171102
* Fix 80 column violation.Craig Topper2012-12-261-2/+2
| | | | llvm-svn: 171097
* Fix class name in comment.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171096
* Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.Craig Topper2012-12-261-62/+12
| | | | llvm-svn: 171095
* Remove 'v' from mnemonic to fix asm matching failures.Craig Topper2012-12-261-1/+1
| | | | llvm-svn: 171093
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-108/+42
| | | | | | definitions for a bunch of SSE2 integer arithmetic instructions. llvm-svn: 171092
* Reformat the docs.Nadav Rotem2012-12-261-20/+7
| | | | llvm-svn: 171091
* Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction ↵Craig Topper2012-12-261-30/+18
| | | | | | definitions for PAND/POR/PXOR/PANDN llvm-svn: 171087
* Merge an AVX/SSE 256-bit and 128-bit multiclass.Craig Topper2012-12-261-26/+15
| | | | llvm-svn: 171086
* Mark VANDNPD/VANDNPDS as not commutable.Craig Topper2012-12-261-1/+2
| | | | llvm-svn: 171085
* Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper2012-12-261-47/+47
| | | | llvm-svn: 171082
* Remove alignment from folding table for VMOVUPD as an unaligned instruction ↵Craig Topper2012-12-261-1/+1
| | | | | | it shouldn't require alignment... llvm-svn: 171081
* Remove alignment requirements from (V)EXTRACTPS. This instruction does ↵Craig Topper2012-12-261-2/+2
| | | | | | 32-bit stores which aren't required to be aligned on SSE or AVX. llvm-svn: 171080
* Remove alignment requirement from VCVTSS2SD in folding tables. Reverting ↵Craig Topper2012-12-261-2/+2
| | | | | | r171049. This instruction doesn't require alignment. llvm-svn: 171078
* Expand PPC64 atomic load and storeHal Finkel2012-12-251-0/+2
| | | | | | | | Use of store or load with the atomic specifier on 64-bit types would cause instruction-selection failures. As with the 32-bit case, these can use the default expansion in terms of cmp-and-swap. llvm-svn: 171072
* X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use ↵Benjamin Kramer2012-12-251-6/+4
| | | | | | of and commutativity. llvm-svn: 171064
* X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.Benjamin Kramer2012-12-251-2/+24
| | | | | | | pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack. Small speedup on loop-vectorized viterbi (-march=core2). llvm-svn: 171063
OpenPOWER on IntegriCloud