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* Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes2011-01-202-5/+9
| | | | llvm-svn: 123936
* Change instruction names for consistencyBruno Cardoso Lopes2011-01-201-4/+6
| | | | llvm-svn: 123930
* Add cdp/cdp2 instructions for thumb/thumb2Bruno Cardoso Lopes2011-01-203-1/+51
| | | | llvm-svn: 123929
* - Use a more appropriate name for Owen's ARM Parser isMCR hack since the ↵Bruno Cardoso Lopes2011-01-202-26/+60
| | | | | | | | | | same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
* Add mcr*2 and mr*c2 support to thumb2 targetsBruno Cardoso Lopes2011-01-202-0/+62
| | | | llvm-svn: 123919
* Add mcr* and mr*c support to thumb targetsBruno Cardoso Lopes2011-01-203-2/+68
| | | | llvm-svn: 123917
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-202-1/+7
| | | | llvm-svn: 123912
* Refactor mcr* and mr*c instructions into classes with the same encoding. No ↵Bruno Cardoso Lopes2011-01-201-108/+46
| | | | | | functionality change. llvm-svn: 123910
* Correct itinerary entry for t2MOV_pic_ga_add_pc.Evan Cheng2011-01-201-1/+1
| | | | llvm-svn: 123907
* Sorry, several patches in one.Evan Cheng2011-01-2012-168/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju2011-01-202-8/+225
| | | | | | with useful instructions. llvm-svn: 123884
* Fix the encoding of mrrc and mcrr family of instructions. Also add testcases ↵Bruno Cardoso Lopes2011-01-191-16/+16
| | | | | | for mcr and mrc llvm-svn: 123837
* ARM/ISel: Factor out isScaledConstantInRange() helper.Daniel Dunbar2011-01-191-122/+110
| | | | llvm-svn: 123823
* For ARM subtargets with useNEONForSinglePrecisionFP, double count usesAndrew Trick2011-01-191-0/+16
| | | | | | | | of the floating point types less than 64-bits. It's somewhat of a temporary hack but forces more accurate modeling of register pressure and results in fewer spills. llvm-svn: 123811
* whitespaceAndrew Trick2011-01-191-16/+16
| | | | llvm-svn: 123810
* Don't forget to emit the load from indirect symbol when using movw + movt to ↵Evan Cheng2011-01-194-6/+14
| | | | | | materialize GA indirect symbols. llvm-svn: 123809
* Create two new generic classes to represent the following VMRS/VMSR variations:Bruno Cardoso Lopes2011-01-182-30/+55
| | | | | | | | | vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783
* Fix MRS encoding for arm and thumb.Bruno Cardoso Lopes2011-01-182-4/+9
| | | | llvm-svn: 123778
* Fix the encoding of t2ISB by using the right class and also parse it correctlyBruno Cardoso Lopes2011-01-182-2/+2
| | | | llvm-svn: 123776
* Follow the current hack set and enable the correct parsing of bkpt while in ↵Bruno Cardoso Lopes2011-01-181-3/+9
| | | | | | thumb mode. llvm-svn: 123772
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-184-13/+79
| | | | | | instruction llvm-svn: 123770
* Add a FIXME.Jim Grosbach2011-01-181-0/+1
| | | | llvm-svn: 123769
* Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa ↵Bruno Cardoso Lopes2011-01-182-0/+9
| | | | | | Stankovic llvm-svn: 123768
* Negative zero is not legal on mips. Patch by Sasa StankovicBruno Cardoso Lopes2011-01-181-0/+2
| | | | llvm-svn: 123766
* Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa StankovicBruno Cardoso Lopes2011-01-181-3/+2
| | | | llvm-svn: 123763
* Add support for mips32 madd and msub instructions. Patch by Akira HatanakaBruno Cardoso Lopes2011-01-183-10/+229
| | | | llvm-svn: 123760
* add a noteChris Lattner2011-01-181-0/+20
| | | | llvm-svn: 123752
* SPARC backend: Modified LowerCall and LowerFormalArguments so that they use ↵Venkatraman Govindaraju2011-01-182-272/+221
| | | | | | CallingConv assignments. llvm-svn: 123749
* McARM: Use accessors where appropriate.Daniel Dunbar2011-01-181-13/+13
| | | | llvm-svn: 123746
* McARM: Fill in ASMOperand::dump() for memory operands.Daniel Dunbar2011-01-181-1/+56
| | | | llvm-svn: 123745
* McARM: Make ARMOperand use a union where appropriate.Daniel Dunbar2011-01-181-9/+13
| | | | llvm-svn: 123744
* McARM: Unify ParseMemory() successfull return.Daniel Dunbar2011-01-181-40/+22
| | | | llvm-svn: 123740
* McARM: Early exit on failure (NEFC).Daniel Dunbar2011-01-181-7/+8
| | | | llvm-svn: 123739
* McARM: Always keep an offset expression, if used (instead of assuming == 0 ↵Daniel Dunbar2011-01-181-24/+29
| | | | | | | | if used but not present), and simplify logic. Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb(). llvm-svn: 123738
* McARM: Add a variety of asserts on the sanity of memory operands.Daniel Dunbar2011-01-181-1/+10
| | | | llvm-svn: 123737
* McARM: Use a consistent marker for not-set OffsetRegNum.Daniel Dunbar2011-01-181-1/+1
| | | | llvm-svn: 123736
* McARM: Start marking T2 address operands as such, for the benefit of the parser.Daniel Dunbar2011-01-181-0/+5
| | | | llvm-svn: 123722
* The stub routine that we're calling uses test and so clobbersEric Christopher2011-01-181-2/+2
| | | | | | the flags. llvm-svn: 123712
* minor change to rafael's recent patches: if something isChris Lattner2011-01-181-1/+7
| | | | | | | constant but requires a unique address, we can still put it in a readonly section, just not a mergable one. llvm-svn: 123711
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-184-16/+0
| | | | llvm-svn: 123707
* Add a missing <cctype> include, from Joerg Sonnenberger!Douglas Gregor2011-01-171-0/+1
| | | | llvm-svn: 123670
* Split up RotateShift itinerary in SPU.Kalle Raiskila2011-01-172-38/+40
| | | | | | | | 'rotq*' and 'shlq*' instructions go to the odd pipeline, wheras the inter-vector equivalents 'rot*', 'shl*' go to the even. llvm-svn: 123622
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-4/+4
| | | | llvm-svn: 123620
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-1715-81/+244
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Provide instruction sizes for ARMv5 variants of MUL instructions.Anton Korobeynikov2011-01-161-29/+30
| | | | | | This fixes PR8987 llvm-svn: 123598
* Update README.txt to remove the DAE enhancement.Anders Carlsson2011-01-161-23/+0
| | | | llvm-svn: 123597
* Only put unnamed_addr constants in mergeable sections. Fixes PR8297.Rafael Espindola2011-01-161-1/+1
| | | | llvm-svn: 123585
* fix PR8514, a bug where the "heroic" transformation of shift/and Chris Lattner2011-01-161-13/+9
| | | | | | | | into and/shift would cause nodes to move around and a dangling pointer to happen. The code tried to avoid this with a HandleSDNode, but got the details wrong. llvm-svn: 123578
* add some commentaryChris Lattner2011-01-161-1/+14
| | | | llvm-svn: 123572
* Spill R4 if it's going to be used to restore SP from FP.Evan Cheng2011-01-161-4/+12
| | | | llvm-svn: 123567
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