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* Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because theNadav Rotem2011-10-101-11/+3
| | | | | | instruction set has no 64-bit SRA support. llvm-svn: 141570
* X86: Add patterns for the movbe instruction (mov + bswap, only available on ↵Benjamin Kramer2011-10-103-12/+13
| | | | | | atom) llvm-svn: 141563
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-104-165/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-101-2/+11
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Put a bunch of calls to ToggleFeature behind proper if statements.Craig Topper2011-10-101-17/+42
| | | | llvm-svn: 141527
* Fix a regression from r138445. If we're loading from the frame/base pointerChad Rosier2011-10-101-0/+1
| | | | | | | | the tADDrSPi instruction can't be used. Make sure we're updating the opcode to tADDi3 in all cases. rdar://10254707 llvm-svn: 141523
* PTX: Print .ptr kernel attributes if PTX version >= 2.2Justin Holewinski2011-10-094-1/+49
| | | | llvm-svn: 141508
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-095-3/+42
| | | | | | disassembler. llvm-svn: 141505
* Prevent potential NOREX bug.Jakob Stoklund Olesen2011-10-081-0/+11
| | | | | | | | | | | | | | | A GR8_NOREX virtual register is created when extrating a sub_8bit_hi sub-register: %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1 TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2 If such a live range is ever split, its register class must not be inflated to GR8. The sub-register copy can only target GR8_NOREX. I dont have a test case for this theoretical bug. llvm-svn: 141500
* Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.Jakob Stoklund Olesen2011-10-083-3/+13
| | | | | | | | | | | | | In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. llvm-svn: 141499
* Always check if a method or a type exist before trying to create it.Nicolas Geoffray2011-10-081-12/+23
| | | | llvm-svn: 141490
* Disable ABS optimization for Thumb1 target, we don't have necessary ↵Anton Korobeynikov2011-10-081-0/+3
| | | | | | instructions there. llvm-svn: 141481
* Simplify definition of FP move instructions.Akira Hatanaka2011-10-082-5/+6
| | | | llvm-svn: 141476
* Define classes and multiclasses for FP binary instructions.Akira Hatanaka2011-10-082-15/+15
| | | | llvm-svn: 141475
* Define multiclasses for FP-to-FP instructions.Akira Hatanaka2011-10-081-11/+11
| | | | llvm-svn: 141474
* Define classes for FP unary instructions and multiclasses for FP-to-fixed pointAkira Hatanaka2011-10-082-65/+66
| | | | | | conversion instructions. llvm-svn: 141473
* Add patterns for unaligned load and store instructions and enable theAkira Hatanaka2011-10-082-46/+76
| | | | | | instruction selector to generate them. llvm-svn: 141471
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-075-14/+173
| | | | llvm-svn: 141446
* ARM prefix asmparser operand kind enums for readability.Jim Grosbach2011-10-071-172/+172
| | | | llvm-svn: 141438
* Take all of the invoke basic blocks and make the dispatch basic block their newBill Wendling2011-10-071-4/+28
| | | | | | | | | | | successor. Remove the old landing pad from their successor list, because it's now the successor of the dispatch block. Now that the landing pad blocks are no longer the destination of invokes, we can mark them as normal basic blocks instead of landing pads. This more closely resembles what the CFG is actually doing. llvm-svn: 141436
* Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emitBill Wendling2011-10-072-0/+52
| | | | | | | it with the new SjLj emitter stuff. This way there's no need to emit that kind-of-hacky intrinsic. llvm-svn: 141419
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-1/+2
| | | | | | do. This will be useful later on with the new SJLJ stuff. llvm-svn: 141416
* Constrain both operands on MOVZX32_NOREXrr8.Jakob Stoklund Olesen2011-10-072-4/+7
| | | | | | | | | | | | This instruction is explicitly encoded without an REX prefix, so both operands but be *_NOREX. Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX constraints are not satisfied. This fixes a miscompilation in 20040709-2 in the gcc test suite. llvm-svn: 141410
* Improve ARM assembly parser diagnostic for unexpected tokens.Jim Grosbach2011-10-071-1/+2
| | | | | | | | | | | | | | | | | Consider: mov r8, r11 fred Previously, we issued the not very informative: x.s:6:1: error: unexpected token in argument list ^ Now we generate: x.s:5:14: error: unexpected token in argument list mov r8, r11 fred ^ llvm-svn: 141380
* High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336Evan Cheng2011-10-071-0/+27
| | | | llvm-svn: 141371
* Reenable tail calls for iOS 5.0 and later.Bob Wilson2011-10-073-2/+11
| | | | llvm-svn: 141370
* Reenable use of divmod compiler_rt functions for iOS 5.0 and later.Bob Wilson2011-10-071-0/+7
| | | | llvm-svn: 141368
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-074-0/+162
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.Craig Topper2011-10-071-0/+23
| | | | llvm-svn: 141358
* Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.Craig Topper2011-10-071-0/+15
| | | | llvm-svn: 141354
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-072-21/+16
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
* Use the correct vreg here.Bill Wendling2011-10-061-1/+1
| | | | llvm-svn: 141342
* Generate the dispatch code for a 'thumb' function. This is very similar to theBill Wendling2011-10-061-2/+53
| | | | | | | others. They take the call site value. Determine if it's a proper value. And then jumps to the correct call site via a jump table. llvm-svn: 141341
* Fix the check for nested IT instructions in the disassembler. We need to ↵Owen Anderson2011-10-061-3/+6
| | | | | | perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. llvm-svn: 141339
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-061-4/+0
| | | | | | with this patch. llvm-svn: 141333
* Generate the dispatch table for ARM mode.Bill Wendling2011-10-061-29/+71
| | | | llvm-svn: 141327
* Refactor some of the code that sets up the entry block for SjLj EH. No ↵Bill Wendling2011-10-062-79/+105
| | | | | | functionality change. llvm-svn: 141323
* Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)Bill Wendling2011-10-061-7/+12
| | | | | | Place the immediate to OR into a register so that it works. llvm-svn: 141319
* * Set the low bit of the return address when we are in thumb mode.Bill Wendling2011-10-061-73/+90
| | | | | | * Some code cleanup. llvm-svn: 141317
* PTX: Implement signed divisionJustin Holewinski2011-10-061-5/+34
| | | | llvm-svn: 141306
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-062-3/+25
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Build system infrastructure for multiple tblgens.Peter Collingbourne2011-10-0613-97/+97
| | | | llvm-svn: 141266
* Add the MBBs before inserting the instructions. Doing it afterwards could leadBill Wendling2011-10-061-28/+10
| | | | | | | | to an infinite loop because of the def-use chains. Also use a frame load instead of store for the LD instruction. llvm-svn: 141263
* Always merge profitable shifts on A9, not just when they have a single use.Cameron Zwarich2011-10-051-6/+2
| | | | llvm-svn: 141248
* Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich2011-10-051-10/+0
| | | | | | | | merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. llvm-svn: 141247
* Get the proper call site numbers for the landing pads. Also remove a magicBill Wendling2011-10-051-15/+27
| | | | | | number (18) for the proper addressing mode. llvm-svn: 141245
* Override TRI::getSubClassWithSubReg for X86.Jakob Stoklund Olesen2011-10-052-0/+15
| | | | | | | | There are fewer registers with sub_8bit sub-registers in 32-bit mode than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as sub_8bit_hi. llvm-svn: 141206
* PTX: Fixup a case where getRegClassFor() should be used instead of custom code.Justin Holewinski2011-10-051-17/+1
| | | | llvm-svn: 141199
* Fix assertion string.Akira Hatanaka2011-10-051-1/+1
| | | | llvm-svn: 141197
* Make sure candidate for delay slot filler is not a return instruction.Akira Hatanaka2011-10-051-3/+5
| | | | llvm-svn: 141196
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