summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Fix .fpu printing in ARM assembly, regarding bug ↵Renato Golin2011-02-281-4/+38
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=8931 llvm-svn: 126689
* Add missing whitespace in the formatting.Kevin Enderby2011-02-281-1/+1
| | | | llvm-svn: 126687
* fix a signed comparison warning.Chris Lattner2011-02-281-1/+1
| | | | llvm-svn: 126682
* [AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bitDavid Greene2011-02-284-30/+120
| | | | | | | | and 256-bit forms. Because the number of elements in a vector does not determine the vector type (4 elements could be v4f32 or v4f64), pass the full type of the vector to decode routines. llvm-svn: 126664
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-1/+13
| | | | | | needed two predicate operands before the imm operand. llvm-svn: 126662
* Fix a typo which cause dag combine crash. rdar://9059537.Evan Cheng2011-02-281-1/+1
| | | | llvm-svn: 126661
* Support for byval parameters on ARM. Will be enabled by a forthcomingStuart Hastings2011-02-283-9/+47
| | | | | | patch to the front-end. Radar 7662569. llvm-svn: 126655
* Add branch hinting for SPU. Kalle Raiskila2011-02-284-5/+94
| | | | | | | The implemented algorithm is overly simplistic (just speculate all branches are taken)- this is work in progress. llvm-svn: 126651
* Add preliminary support for .f32 in the PTX backend.Che-Liang Chiou2011-02-285-10/+131
| | | | | | | | | | | | - Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski llvm-svn: 126636
* Silence enum conversion warnings.Benjamin Kramer2011-02-271-2/+2
| | | | llvm-svn: 126578
* Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit ↵NAKAMURA Takumi2011-02-271-17/+39
| | | | | | | | "spill/reload frames" for XMMs. It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs). llvm-svn: 126568
* Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer2011-02-261-37/+0
| | | | | | | | | | | legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. llvm-svn: 126557
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-2516-157/+161
| | | | | | the type of the LHS. llvm-svn: 126518
* Roll out r126425 and r126450 to see if it fixes the failures on the buildbots.Cameron Zwarich2011-02-254-11/+1
| | | | llvm-svn: 126488
* Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson2011-02-253-11/+39
| | | | llvm-svn: 126477
* Fix typo.Evan Cheng2011-02-251-1/+1
| | | | llvm-svn: 126467
* Each prologue may have multiple vpush instructions to store callee-savedEvan Cheng2011-02-251-2/+14
| | | | | | | | | | | D registers since the vpush list may not have gaps. Make sure the stack adjustment instruction isn't moved between them. Ditto for vpop in epilogues. Sorry, can't reduce a small test case. rdar://9043312 llvm-svn: 126457
* remove command line option debugging hook.Chris Lattner2011-02-241-6/+0
| | | | llvm-svn: 126441
* Enable DebugInfo support for COFF object files.Devang Patel2011-02-244-1/+11
| | | | | | Patch by Nathan Jeffords! llvm-svn: 126425
* Add XCore intrinsic for eeu instruction.Richard Osborne2011-02-241-0/+4
| | | | llvm-svn: 126384
* Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memoryEvan Cheng2011-02-241-2/+2
| | | | | | | | operands starts at index 2, not 1. rdar://9045024 PR9305 llvm-svn: 126359
* Add XCore intrinsic for clre instruction.Richard Osborne2011-02-231-1/+3
| | | | llvm-svn: 126322
* Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enableRichard Osborne2011-02-231-1/+7
| | | | | | | events on the thread and wait until a resource is ready to event. The vector of the resource that is ready is returned. llvm-svn: 126320
* Add XCore intrinsic for the setv instruction.Richard Osborne2011-02-231-1/+6
| | | | llvm-svn: 126315
* Fix format for setc instruction.Richard Osborne2011-02-231-1/+1
| | | | llvm-svn: 126314
* Add XCore intrinsic for settw instruction.Richard Osborne2011-02-231-1/+5
| | | | llvm-svn: 126313
* Change VFPNeonA8 definition to make the code easier to read.Evan Cheng2011-02-232-8/+3
| | | | llvm-svn: 126298
* More fcopysign correctness and performance fix.Evan Cheng2011-02-231-33/+63
| | | | | | | | | | | | | The previous codegen for the slow path (when values are in VFP / NEON registers) was incorrect if the source is NaN. The new codegen uses NEON vbsl instruction to copy the sign bit. e.g. vmov.i32 d1, #0x80000000 vbsl d1, d2, d0 If NEON is not available, it uses integer instructions to copy the sign bit. rdar://9034702 llvm-svn: 126295
* [AVX] General VUNPCKL codegen support.David Greene2011-02-222-0/+20
| | | | llvm-svn: 126264
* Use the same (%dx) hack for in[bwl] as for out[bwl].Joerg Sonnenberger2011-02-221-0/+13
| | | | llvm-svn: 126244
* VFP single precision arith instructions can go down to NEON pipeline, but on ↵Evan Cheng2011-02-226-109/+114
| | | | | | Cortex-A8 only. llvm-svn: 126238
* Stack alignment is 16 bytes on FreeBSD/i386 too.Roman Divacky2011-02-222-3/+5
| | | | llvm-svn: 126226
* Guard against de-referencing MBB.end().Evan Cheng2011-02-221-1/+4
| | | | llvm-svn: 126192
* available_externally (hidden or not) GVs are always accessed via stubs. ↵Evan Cheng2011-02-221-1/+3
| | | | | | rdar://9027648. llvm-svn: 126191
* Only use blx for external function calls on thumb, these could be fixedEric Christopher2011-02-221-12/+26
| | | | | | | | | up by the dynamic linker, but it's better to use the correct instruction to begin with. Fixes rdar://9011034 llvm-svn: 126176
* Recognize loopz and loopnz as aliases for loope and loopne.Joerg Sonnenberger2011-02-221-0/+3
| | | | | | From Dimitry Andric. llvm-svn: 126168
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-224-0/+19
| | | | | | Patch by Jai Menon. llvm-svn: 126165
* Skipping over debugvalue instructions to determine whether the split spot is ↵Evan Cheng2011-02-211-0/+3
| | | | | | in a IT block. rdar://9030770 llvm-svn: 126159
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-216-25/+25
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Fixed a bug in the X86 disassembler where a member of theSean Callanan2011-02-212-5/+5
| | | | | | | | X86 instruction decode structure was being interpreted as being in units of bits, although it is actually stored in units of bytes. llvm-svn: 126147
* Add XCore intrinsics for various instructions on ports.Richard Osborne2011-02-211-2/+24
| | | | llvm-svn: 126132
* The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.Duncan Sands2011-02-212-3/+4
| | | | llvm-svn: 126130
* a serious "compare CSE" issue that is nontrivial to get right,Chris Lattner2011-02-211-0/+69
| | | | | | but which is responsible for us doing really bad things to 256.bzip2. llvm-svn: 126126
* Target/X86/X86FastISel: [PR6275] Fix Win32's dllimport function with fastisel.NAKAMURA Takumi2011-02-211-2/+6
| | | | | | | "dllimport" function must not be GlobalVariable, but Function. It is enough to check with GlobalValue. test/CodeGen/X86/dll-linkage.ll is updated to check llc -O0. llvm-svn: 126110
* Generate correct Sparc32 ABI compliant code for functions that return a struct.Venkatraman Govindaraju2011-02-214-8/+84
| | | | llvm-svn: 126108
* add a missed loop deletion case.Chris Lattner2011-02-211-0/+14
| | | | llvm-svn: 126103
* add an idiom that loop idiom could theoretically catch.Chris Lattner2011-02-211-0/+10
| | | | llvm-svn: 126101
* A lo/hi mul has higher latency than an imul r,ri, e.g. 5 cycles compared to 3Cameron Zwarich2011-02-211-35/+0
| | | | | | on Core 2 and Nehalem, so the code we generate is better than GCC's here. llvm-svn: 126100
* The signed version of our "magic number" computation for the integer ↵Cameron Zwarich2011-02-211-6/+4
| | | | | | | | | | | | | approximation of a constant had a minor typo introduced when copying it from the book, which caused it to favor negative approximations over positive approximations in many cases. Positive approximations require fewer operations beyond the multiplication. In the case of division by 3, we still generate code that is a single instruction larger than GCC's code. llvm-svn: 126097
* If both operands are loads from stores in memory we can't use movlpd/movlpsEric Christopher2011-02-201-0/+4
| | | | | | | | | since one needs to be a register operand. Just use movss instead of forcing an operand into a register. Fixes PR9239 llvm-svn: 126072
OpenPOWER on IntegriCloud