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* Remove a non-modular header (& inline it into its one use)David Blaikie2017-12-142-68/+55
| | | | llvm-svn: 320768
* [AArch64] Test patchEvandro Menezes2017-12-141-0/+1
| | | | | | Fix formatting by adding a missing blank line to test new network setup. llvm-svn: 320760
* [X86] Remove an unnecessary SmallVector that was collecting chains for two ↵Craig Topper2017-12-141-5/+3
| | | | | | | | SDNode's we're still holding SDValues for. NFCI We can just get the chains from those SDValues to create the TokenFactor. llvm-svn: 320757
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-1414-1/+15
| | | | llvm-svn: 320756
* Fix many -Wsign-compare and -Wtautological-constant-compare warnings.Zachary Turner2017-12-141-1/+1
| | | | | | | | | | | | Most of the -Wsign-compare warnings are due to the fact that enums are signed by default in the MS ABI, while the tautological comparison warnings trigger on x86 builds where sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max() is always false. Differential Revision: https://reviews.llvm.org/D41256 llvm-svn: 320750
* [SimplifyCFG] don't sink common insts too soon (PR34603)Sanjay Patel2017-12-142-2/+2
| | | | | | | | | | | | This should solve: https://bugs.llvm.org/show_bug.cgi?id=34603 ...by preventing SimplifyCFG from altering redundant instructions before early-cse has a chance to run. It changes the default (canonical-forming) behavior of SimplifyCFG, so we're only doing the sinking transform later in the optimization pipeline. Differential Revision: https://reviews.llvm.org/D38566 llvm-svn: 320749
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-147-123/+62
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-145-7/+111
| | | | llvm-svn: 320744
* [X86] Don't zero the upper bits of the k-register before extracting a single ↵Craig Topper2017-12-141-6/+3
| | | | | | | | bit from a vXi1. This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway. llvm-svn: 320723
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-145-69/+24
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.Geoff Berry2017-12-141-1/+3
| | | | | | Fixes expensive-check ARM buildbot failure. llvm-svn: 320718
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-141-11/+8
| | | | | | This commit might have caused regression on ppc64. Revert it to verify that. llvm-svn: 320712
* Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
* [mips] Add partial support for R6 in the long branch passSimon Dardis2017-12-141-46/+116
| | | | | | | | | | | | | | | | | | | | MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
* Any Target Asm comments should start from MachineInstr::TAsmComments value.Andrew V. Tischenko2017-12-141-1/+4
| | | | llvm-svn: 320693
* [AVX512] Adding support for load truncate store of I1Michael Zuckerman2017-12-141-0/+3
| | | | | | | | | | store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion. This patch fixes this issue. Differential Revision: https://reviews.llvm.org/D39547 Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9 llvm-svn: 320691
* Remove redundant includes from lib/Target/AArch64.Fedor Sergeev2017-12-141-1/+0
| | | | llvm-svn: 320686
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-144-25/+25
| | | | | | | | | | | | Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. llvm-svn: 320682
* [X86] Make ANY_EXTEND from vXi1 Custom for more types.Craig Topper2017-12-141-0/+6
| | | | | | We should be able to support ANY_EXTEND for any types we support ZERO_EXTEND for. llvm-svn: 320675
* [X86] Remove redundant setOperationAction calls.Craig Topper2017-12-141-2/+0
| | | | | | These calls already exist earlier under AVX2 feature. llvm-svn: 320673
* Recommit r320461 "[X86] Use regular expressions more aggressively to reduce ↵Craig Topper2017-12-134-1032/+48
| | | | | | | | | | | | | | the number of scheduler entries needed for FMA3 instructions." I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name. Original commit message: When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320655
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-131-8/+11
| | | | | | | | | | | | | | | | | Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
* Recover some overzealously removed includes.Michael Zolotukhin2017-12-133-0/+3
| | | | llvm-svn: 320648
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-1312-31/+0
| | | | llvm-svn: 320636
* Remove redundant includes from lib/Target/ARM.Michael Zolotukhin2017-12-138-17/+0
| | | | llvm-svn: 320635
* Remove redundant includes from lib/Target/AArch64.Michael Zolotukhin2017-12-137-13/+0
| | | | llvm-svn: 320634
* Remove redundant includes from lib/Target/*.cpp.Michael Zolotukhin2017-12-133-5/+0
| | | | llvm-svn: 320633
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-138-78/+128
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* Fix link failure on one build bot introduced by r320584.Nemanja Ivanovic2017-12-131-1/+3
| | | | llvm-svn: 320589
* Reverted r320229. It broke tests on builder ↵Galina Kistanova2017-12-131-118/+4
| | | | | | llvm-clang-x86_64-expensive-checks-win. llvm-svn: 320588
* [PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic2017-12-135-0/+740
| | | | | | | | | | | | | | The initial implementation of an MI SSA pass to reduce cr-logical operations. Currently, the only operations handled by the pass are binary operations where both CR-inputs come from the same block and the single use is a conditional branch (also in the same block). Committing this off by default to allow for a period of field testing. Will enable it by default in a follow-up patch soon. Differential Revision: https://reviews.llvm.org/D30431 llvm-svn: 320584
* [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule testsSimon Pilgrim2017-12-133-1/+4
| | | | | | Add missing RDTSCP itinerary llvm-svn: 320581
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-131-0/+3
| | | | | | | | Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. llvm-svn: 320575
* [X86][SSE] MOVMSK only uses the sign bit from each vector elementSimon Pilgrim2017-12-131-0/+22
| | | | | | | | | | Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK We'd probably get more hits if SimplifyDemandedBits was better at handling vectors... Differential Revision: https://reviews.llvm.org/D41119 llvm-svn: 320570
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-132-0/+46
| | | | | | | | | | | | | | | Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. llvm-svn: 320569
* [mips] Provide additional DSP bitconvert patternsStefan Maksimovic2017-12-131-0/+4
| | | | | | | | | Previously, v2i16 -> f32 bitcast could not be matched. Add patterns to support matching this and similar types of bitcasts. Differential revision: https://reviews.llvm.org/D40959 llvm-svn: 320562
* [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming ↵Alex Bradbury2017-12-132-98/+100
| | | | | | | | | | | | | | convention When an instruction mnemonic contains a '.', we usually name the instruction with a _ in that place. e.g. fadd.s -> FADD_S. This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP. Also includes some minor formatting changes in RISCVInstrInfoC.td to better align it with the formatting conventions in the rest of the backend. llvm-svn: 320560
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-132-22/+22
| | | | | | | We sort these helper functions and td definitions by bit width. simm6 was previously out-of-order with respect to the others. llvm-svn: 320559
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-135-20/+390
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [Targets] Don't automatically include the scheduler class enum from ↵Craig Topper2017-12-133-0/+4
| | | | | | | | | | *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately. Most of the targets don't need the scheduler class enum. I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86. llvm-svn: 320552
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-1325-24/+26
| | | | | | | | | | Headers/Implementation files should be named after the class they declare/define. Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in favor of `class LiveIntarvals;` llvm-svn: 320546
* [Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek2017-12-121-3/+17
| | | | llvm-svn: 320523
* [Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek2017-12-121-1/+1
| | | | | | | | | | | | Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. llvm-svn: 320516
* Reapply "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-121-0/+3
| | | | | | | This reverts commit r320508, in effect re-applying r320308. Simon has already reverted the parts that caused the crash that motivated the revert in r320492. llvm-svn: 320512
* Revert "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-121-3/+0
| | | | | | | This reverts commit r320308. r320308 crashes LLC, please see the llvm-commits thread for a reproducer. llvm-svn: 320508
* [X86] Add a couple TODOs about missing coverage/features motivated by D40335Craig Topper2017-12-121-0/+4
| | | | | | D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code. llvm-svn: 320507
* [X86] Cleanup type conversion of 64-bit load-store pairs.Nirav Dave2017-12-121-41/+14
| | | | | | | | | | | | | | | | Summary: Simplify and generalize chain handling and search for 64-bit load-store pairs. Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs. Reviewers: craig.topper, spatel Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40918 llvm-svn: 320505
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-123-8/+25
| | | | | | | | | | | | | | | | | | Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
* [X86] Remove CompleteModel tags from CPU targets until we have better error ↵Simon Pilgrim2017-12-124-0/+18
| | | | | | | | | | checking (PR35636) The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW Raised PR35639 and PR35643 as examples llvm-svn: 320492
* [RISCV][NFC] Formatting fix in RISCVInstrInfo.tdAlex Bradbury2017-12-121-4/+4
| | | | llvm-svn: 320491
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