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* Refactor load/store handling again. Simplify and make some room forEric Christopher2010-12-011-103/+60
| | | | | | reg+reg handling. llvm-svn: 120526
* Initialize an ARMConstantPoolValue field.Jan Wen Voung2010-12-011-1/+1
| | | | llvm-svn: 120525
* s/T1pIEncode/T1pILdStEncode/gBill Wendling2010-12-012-62/+62
| | | | | | s/T1pIEncodeImm/T1pILdStEncodeImm/g llvm-svn: 120524
* Renaming variables to coincide with documentation. No functionality change.Bill Wendling2010-12-012-21/+21
| | | | llvm-svn: 120522
* Refactor T1sI and T1sIt encodings into helper classes.Bill Wendling2010-12-011-93/+78
| | | | llvm-svn: 120518
* Refactor the T1sIt encodings into a parent class to get rid of all of the "let"Bill Wendling2010-12-011-131/+85
| | | | | | statements. llvm-svn: 120512
* Use by-name rather than by-order matching for NEON operands.Owen Anderson2010-12-011-318/+318
| | | | llvm-svn: 120507
* Enable sibling call optimization of libcalls which are expanded duringEvan Cheng2010-11-307-62/+112
| | | | | | | | | | | legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
* Rename operands to match ARM documentation. No functionality change.Bill Wendling2010-11-302-101/+105
| | | | llvm-svn: 120500
* Fix typo.Jim Grosbach2010-11-301-1/+1
| | | | llvm-svn: 120499
* Trailing whitespace.Jim Grosbach2010-11-301-3/+3
| | | | llvm-svn: 120497
* Thanks to JimG for catching this!Jason W Kim2010-11-301-0/+2
| | | | llvm-svn: 120494
* Inline classes that were used in only one place.Bill Wendling2010-11-301-5/+2
| | | | llvm-svn: 120488
* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-305-90/+151
| | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. llvm-svn: 120482
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-304-88/+16
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Fix handling of ARM negative pc-relative fixups for loads and stores.Jim Grosbach2010-11-302-9/+36
| | | | llvm-svn: 120480
* Move X86InstrFPStack.td over to PseudoI as well.Eric Christopher2010-11-301-27/+9
| | | | llvm-svn: 120470
* Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violationsEric Christopher2010-11-301-19/+15
| | | | | | while I'm in there. llvm-svn: 120466
* Provide Thumb2 encodings for a few miscellaneous instructions.Owen Anderson2010-11-301-8/+22
| | | | llvm-svn: 120455
* Add FIXMEJim Grosbach2010-11-301-0/+1
| | | | llvm-svn: 120451
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-303-1/+43
| | | | llvm-svn: 120449
* Noticed this on inspection, fix and update some comments.Eric Christopher2010-11-301-3/+4
| | | | llvm-svn: 120447
* Pseudo-ize ARM MOVPCRXJim Grosbach2010-11-302-8/+19
| | | | llvm-svn: 120442
* Provide encodings for a few more load/store variants.Owen Anderson2010-11-301-4/+16
| | | | llvm-svn: 120439
* Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.Jim Grosbach2010-11-303-46/+66
| | | | | | rdar://8685712 llvm-svn: 120438
* ptx: add command-line options for gpu target and ptx versionChe-Liang Chiou2010-11-301-0/+18
| | | | llvm-svn: 120423
* Fix some grammar in comments I noticed.Eric Christopher2010-11-301-5/+5
| | | | llvm-svn: 120416
* This defaults to GenericDomain.Eric Christopher2010-11-301-1/+1
| | | | llvm-svn: 120415
* Implement a PseudoI class and transfer the sse instructions over to useEric Christopher2010-11-302-12/+15
| | | | | | it. llvm-svn: 120412
* Fix insertion point in pcmp expander.Eric Christopher2010-11-301-9/+2
| | | | | | While I'm there, clean up too many \n even for me. llvm-svn: 120411
* Fix some cleanups from my last patch.Eric Christopher2010-11-302-5/+5
| | | | llvm-svn: 120410
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-304-14/+89
| | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408
* ptx: add ld instructionChe-Liang Chiou2010-11-303-9/+118
| | | | | | | support register and register-immediate addressing mode todo: immediate and register-register addressing mode llvm-svn: 120407
* Rewrite mwait and monitor support and custom lower arguments.Eric Christopher2010-11-303-4/+75
| | | | | | Fixes PR8573. llvm-svn: 120404
* Minor cleanups. No functional change.Bill Wendling2010-11-301-24/+23
| | | | llvm-svn: 120372
* s/ARM::BRIND/ARM::BX/g to coincide with r120366.Bill Wendling2010-11-303-5/+5
| | | | llvm-svn: 120371
* Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn'tBill Wendling2010-11-301-3/+5
| | | | | | able to match this yet. llvm-svn: 120369
* Rename BX/BRIND/etc patterns to clarify which is actually the BX instructionJim Grosbach2010-11-302-9/+9
| | | | | | and which are pseudos. llvm-svn: 120366
* Add some encoding for the adr instruction. Labels still need to be finished.Bill Wendling2010-11-301-6/+16
| | | | llvm-svn: 120365
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-304-48/+96
| | | | llvm-svn: 120364
* Make a few more ARM pseudo instructions actually use the PseudoInst base class.Jim Grosbach2010-11-301-14/+13
| | | | llvm-svn: 120362
* Predicate encoding should be withing {}s. And general cleanup.Bill Wendling2010-11-302-8/+4
| | | | llvm-svn: 120361
* Predicate encoding should be withing {}s.Bill Wendling2010-11-301-2/+2
| | | | llvm-svn: 120360
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-304-37/+67
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
* Rename VLDnDUP instructions with double-spaced registersBob Wilson2010-11-301-12/+12
| | | | | | in an attempt to make things a little more consistent. llvm-svn: 120357
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-306-1/+104
| | | | | | The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
* Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.Jim Grosbach2010-11-291-9/+6
| | | | llvm-svn: 120354
* Parameterize ARMPseudoInst size property.Jim Grosbach2010-11-292-27/+19
| | | | llvm-svn: 120353
* Add a few missing initializers.Jim Grosbach2010-11-291-2/+2
| | | | llvm-svn: 120350
* Nuke trailing whitespace.Jim Grosbach2010-11-291-3/+3
| | | | llvm-svn: 120344
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