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* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-091-3/+4
| | | | llvm-svn: 161626
* [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).Chad Rosier2012-08-091-3/+19
| | | | | | | | | | This new API will be used by clang to parse ms-style inline asms. One goal of this project is to use this style of inline asm for targets other then x86. Therefore, this API needs to be implemented for non-x86 targets at some point in the future. llvm-svn: 161624
* Another 32 to 64 bit sign extension bug.Jack Carter2012-08-091-1/+1
| | | | | | The fields in the td definition were switched. llvm-svn: 161607
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-095-17/+251
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* This field isn't used anymore, use it with HWEncoding instead.Eric Christopher2012-08-091-4/+4
| | | | llvm-svn: 161564
* Don't use getNextOperandForReg().Jakob Stoklund Olesen2012-08-082-2/+8
| | | | | | | | | This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. llvm-svn: 161542
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-084-9/+9
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
* whitespaceAndrew Trick2012-08-081-1/+1
| | | | llvm-svn: 161469
* X86: enable CSE between CMP and SUBManman Ren2012-08-084-47/+98
| | | | | | | | | | | | | | We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 llvm-svn: 161462
* Don't scan physreg use-def chains looking for a PIC base.Jakob Stoklund Olesen2012-08-081-10/+4
| | | | | | | | | | We can't rematerialize a PIC base after register allocation anyway, and scanning physreg use-def chains is very expensive in a function with many calls. <rdar://problem/12047515> llvm-svn: 161461
* X86 cmp lowering is looking past truncate on the condition node. It should onlyEvan Cheng2012-08-071-6/+16
| | | | | | | | do so when the high bits are known zero. This caused a subtle miscompilation. rdar://12027825 llvm-svn: 161451
* Add a comment about mftb vs. mfspr on PPC.Hal Finkel2012-08-071-0/+4
| | | | | | Thanks to Alex Rosenberg for the suggestion. llvm-svn: 161428
* Revert r161371. Removing the 'const' before Type is a "good thing".Bill Wendling2012-08-071-12/+12
| | | | | | | | --- Reverse-merging r161371 into '.': U include/llvm/Target/TargetData.h U lib/Target/TargetData.cpp llvm-svn: 161394
* The define for 64 bit sign extension neglected to Jack Carter2012-08-071-7/+8
| | | | | | | | | | | | | | | | | | | | initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
* Constify the Type parameter to some methods (which are const anyway).Bill Wendling2012-08-071-12/+12
| | | | llvm-svn: 161371
* Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.Andrew Trick2012-08-071-3/+3
| | | | | | | | | | | This allows codegen passes to query properties like InstrItins->SchedModel->IssueWidth. It also ensure's that computeOperandLatency returns the X86 defaults for loads and "high latency ops". This should have no significant impact on existing schedulers because X86 defaults happen to be the same as global defaults. llvm-svn: 161370
* Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter2012-08-072-0/+4
| | | | | | | | I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. llvm-svn: 161366
* The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter2012-08-062-14/+10
| | | | | | | | | | were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. llvm-svn: 161359
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-064-2/+30
| | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. llvm-svn: 161348
* MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel2012-08-061-2/+2
| | | | | | | | | | | The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! llvm-svn: 161346
* Add support for the OpenBSD for Bitrig.Eric Christopher2012-08-061-3/+4
| | | | | | Patch by David Hill. llvm-svn: 161344
* Remove empty overrides of processFunctionBeforeFrameFinalized().Roman Divacky2012-08-063-10/+0
| | | | llvm-svn: 161328
* Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper2012-08-065-55/+187
| | | | | | custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. llvm-svn: 161318
* Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper2012-08-052-24/+2
| | | | | | represented in a pattern. llvm-svn: 161306
* Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper2012-08-051-2/+1
| | | | | | for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. llvm-svn: 161305
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-042-1/+8
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. llvm-svn: 161302
* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | llvm-svn: 161301
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov2012-08-041-0/+4
| | | | | | | | | stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. llvm-svn: 161300
* Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov2012-08-041-3/+43
| | | | | | | | classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
* 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka2012-08-032-54/+269
| | | | | | | | | Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. llvm-svn: 161272
* allow 'make CPPFLAGS=<something>' work againGabor Greif2012-08-031-1/+1
| | | | | | | | this makes this hack a bit more bearable for poor souls who need to pass custom preprocessor flags to the build process llvm-svn: 161240
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-036-15/+26
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> llvm-svn: 161232
* Add new getLibFunc method to TargetLibraryInfo.Bob Wilson2012-08-031-37/+56
| | | | | | | | This just provides a way to look up a LibFunc::Func enum value for a function name. Alphabetize the enums and function names so we can use a binary search. llvm-svn: 161231
* [arm-fast-isel] Add support for shl, lshr, and ashr.Jush Lu2012-08-031-0/+62
| | | | llvm-svn: 161230
* Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher2012-08-035-0/+54
| | | | | | | | but somehow managed to be dropped later. Patch by Karel Gardas. llvm-svn: 161226
* ARM: Tidy up. Remove unused template parameters.Jim Grosbach2012-08-021-20/+16
| | | | llvm-svn: 161222
* ARM: More InstAlias refactors to use #NAME#.Jim Grosbach2012-08-021-42/+27
| | | | llvm-svn: 161220
* ARM: Refactor instaliases using TableGen support for #NAME#.Jim Grosbach2012-08-021-31/+23
| | | | | | | | Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. llvm-svn: 161218
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-021-1/+5
| | | | | | | | | | Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 llvm-svn: 161207
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-029-29/+51
| | | | | | of MipsTargetMachine.cpp. llvm-svn: 161191
* Set transient stack alignment in constructor of MipsFrameLowering and re-enableAkira Hatanaka2012-08-021-3/+2
| | | | | | test o32_cc_vararg.ll. llvm-svn: 161189
* Support fpv4 for ARM Cortex-M4.Jiangning Liu2012-08-021-1/+1
| | | | llvm-svn: 161163
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-023-16/+29
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-023-40/+75
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-026-7/+64
| | | | llvm-svn: 161159
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-08-022-0/+83
| | | | | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 llvm-svn: 161152
* X86: mark GATHER instructios as mayLoadManman Ren2012-08-011-1/+1
| | | | llvm-svn: 161143
* ARM: Remove redundant instalias.Jim Grosbach2012-08-011-3/+0
| | | | llvm-svn: 161134
* Clean up formatting.Jim Grosbach2012-08-012-13/+2
| | | | llvm-svn: 161133
* Tidy up.Jim Grosbach2012-08-011-11/+4
| | | | llvm-svn: 161132
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