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* Refactor some of the "disassembly-only" instructions into a base class. ThisBill Wendling2010-11-291-36/+21
| | | | | | reduces some code duplication. llvm-svn: 120326
* Update fastisel for the changes in r120272.Eric Christopher2010-11-291-3/+7
| | | | llvm-svn: 120324
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-295-14/+14
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* Improving the factoring of several instruction encodings.Owen Anderson2010-11-291-89/+51
| | | | llvm-svn: 120317
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-296-0/+93
| | | | llvm-svn: 120312
* Fix copy-and-paste errors in VLD2-dup scheduling itineraries.Bob Wilson2010-11-292-4/+4
| | | | llvm-svn: 120311
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-295-28/+19
| | | | llvm-svn: 120310
* Thumb2 encodings for MSR and MRS.Owen Anderson2010-11-291-10/+24
| | | | llvm-svn: 120309
* Thumb2 encodings for system instructions.Owen Anderson2010-11-291-8/+50
| | | | llvm-svn: 120307
* Thumb2 encodings for branches and IT blocks.Owen Anderson2010-11-291-0/+15
| | | | llvm-svn: 120306
* The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node toJim Grosbach2010-11-291-4/+4
| | | | | | get the pretty-printer. That's handled explicityly by the MC lowering now. llvm-svn: 120305
* I swear I did a make clean and make before committing all this...Michael J. Spencer2010-11-293-3/+3
| | | | llvm-svn: 120304
* Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.Jim Grosbach2010-11-293-43/+95
| | | | llvm-svn: 120303
* Merge System into Support.Michael J. Spencer2010-11-294-4/+4
| | | | llvm-svn: 120298
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-291-2/+5
| | | | | | shiftamount > 7. llvm-svn: 120288
* Enable PostRA scheduling for SPU. Kalle Raiskila2010-11-292-0/+25
| | | | | | | This speeds up selected test cases with up to 5% - no slowdowns observed. llvm-svn: 120286
* Allow machine LICM to do its job on SPU.Kalle Raiskila2010-11-292-1/+9
| | | | | | | -return a sensible value for register pressure -add pattern to 'ila' instrucion llvm-svn: 120285
* Add missing i128 case.Kalle Raiskila2010-11-291-0/+3
| | | | llvm-svn: 120284
* Add more Thumb encodings.Bill Wendling2010-11-291-12/+30
| | | | llvm-svn: 120279
* More Thumb encodings.Bill Wendling2010-11-291-24/+76
| | | | llvm-svn: 120278
* Add Thumb encodings for REV instructions.Bill Wendling2010-11-291-19/+37
| | | | llvm-svn: 120277
* Add more Thumb encodings.Bill Wendling2010-11-291-24/+58
| | | | llvm-svn: 120272
* Make EmitIntValue non virtual.Rafael Espindola2010-11-281-26/+9
| | | | llvm-svn: 120271
* Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.Rafael Espindola2010-11-283-46/+67
| | | | llvm-svn: 120263
* fix PR8686, accepting a 'b' suffix at the end of all the setccChris Lattner2010-11-281-0/+5
| | | | | | | | | | instructions. I choose to handle this with an asmparser hack, though it could be handled by changing all the instruction definitions to allow be "setneb" instead of "setne". The asm parser hack is better in this case, because we want the disassembler to produce setne, not setneb. llvm-svn: 120260
* When emitting a single function with cppgen=function, you don't want to emitNicolas Geoffray2010-11-281-10/+26
| | | | | | | initializers of global variables used in the function. Also make sure to emit the operands of a constant. llvm-svn: 120253
* Move the PTXMCAsmStreamer class to the .cpp file.Rafael Espindola2010-11-283-206/+181
| | | | llvm-svn: 120241
* Define generic 1, 2 and 4 byte pc relative relocations. They are commonRafael Espindola2010-11-286-69/+15
| | | | | | and at least the 4 byte one will be needed to implement the .cfi_* directives. llvm-svn: 120240
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-288-8/+255
| | | | llvm-svn: 120236
* Another minor refactoring for VLD1DUP instructions.Bob Wilson2010-11-281-22/+20
| | | | | | | The op11_8 field is the same for all of them so put it in the instruction classes instead of specifying it separately for each instruction. llvm-svn: 120234
* Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson2010-11-281-1/+2
| | | | llvm-svn: 120233
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-2728-776/+775
| | | | llvm-svn: 120229
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-2724-598/+610
| | | | llvm-svn: 120228
* Lower TLS_addr32 and TLS_addr64.Rafael Espindola2010-11-273-9/+50
| | | | llvm-svn: 120225
* Implement the data16 prefix.Rafael Espindola2010-11-272-1/+4
| | | | llvm-svn: 120224
* Refactor. Set alignment bit in VLD1-dup instruction classes.Bob Wilson2010-11-271-25/+17
| | | | llvm-svn: 120197
* Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson2010-11-275-2/+119
| | | | llvm-svn: 120194
* Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson2010-11-272-8/+8
| | | | | | | | I added these instructions recently but I have no idea where these "1" values in the NextCycles field came from. As far as I can tell now, these instruction stages are clearly intended to overlap. llvm-svn: 120193
* MC/Mach-O: Switch to using MachOFormat.h.Daniel Dunbar2010-11-273-13/+15
| | | | | | - I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another). llvm-svn: 120187
* Remove the unused TheTarget member.Rafael Espindola2010-11-264-4/+5
| | | | llvm-svn: 120168
* Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single ↵Rafael Espindola2010-11-251-24/+8
| | | | | | instruction. llvm-svn: 120147
* Namespacify.Benjamin Kramer2010-11-251-1/+1
| | | | llvm-svn: 120146
* Updating MBlaze .mask and .frame directives to match GCC's output and fixing ↵Wesley Peck2010-11-241-12/+19
| | | | | | regression introduced in 120095 by checking MCStreamer::hasRawTextSupport. llvm-svn: 120097
* 1. Fixing error where basic block labels were not being printed out when ↵Wesley Peck2010-11-245-33/+126
| | | | | | | | | | they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots. 2. Re-adding .mask and .frame directives in printed assembly. 3. Adding .ent and .end directives in printed assembly. 4. Minor cleanups to MBlaze backend. llvm-svn: 120095
* Use i8 as SETCC result type for i1 in SPU.Kalle Raiskila2010-11-241-4/+14
| | | | llvm-svn: 120092
* Allow for 'fcmp ogt' in SPU.Kalle Raiskila2010-11-241-2/+2
| | | | | | Fix by Visa Putkinen! llvm-svn: 120090
* The srem -> urem transform is not safe for any divisor that's not a power of ↵Benjamin Kramer2010-11-231-2/+2
| | | | | | | | | | two. E.g. -5 % 5 is 0 with srem and 1 with urem. Also addresses Frits van Bommel's comments. llvm-svn: 120049
* Move the ARM reloc constants to Support/ELF.hJason W Kim2010-11-232-142/+4
| | | | llvm-svn: 120035
* Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson2010-11-231-13/+109
| | | | | | | We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. llvm-svn: 120034
* InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is ↵Benjamin Kramer2010-11-231-10/+2
| | | | | | | | positive. This allows to transform the rem in "1 << ((int)x % 8);" to an and. llvm-svn: 120028
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