summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach2011-08-163-1/+62
| | | | | | | | | Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. llvm-svn: 137746
* Instead of always leaving the work to the generic legalizer whenBruno Cardoso Lopes2011-08-161-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is no support for native 256-bit shuffles, be more smart in some cases, for example, when you can extract specific 128-bit parts and use regular 128-bit shuffles for them. Example: For this shuffle: shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6> This was expanded to: vextractf128 $1, %ymm1, %xmm2 vpextrq $0, %xmm2, %rax vmovd %rax, %xmm1 vpextrq $1, %xmm2, %rax vmovd %rax, %xmm2 vpunpcklqdq %xmm1, %xmm2, %xmm1 vpextrq $0, %xmm0, %rax vmovd %rax, %xmm2 vpextrq $1, %xmm0, %rax vmovd %rax, %xmm0 vpunpcklqdq %xmm2, %xmm0, %xmm0 vinsertf128 $1, %xmm1, %ymm0, %ymm0 ret Now we get: vshufpd $1, %xmm0, %xmm0, %xmm0 vextractf128 $1, %ymm1, %xmm1 vshufpd $1, %xmm1, %xmm1, %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 llvm-svn: 137733
* ARM .align NOP padding uses different encoding pre-ARMv6.Jim Grosbach2011-08-161-14/+37
| | | | | | Patch by Kristof Beyls and James Malloy. llvm-svn: 137723
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-166-167/+73
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Define function MipsMCInstLower::LowerOperand. Akira Hatanaka2011-08-162-25/+29
| | | | llvm-svn: 137707
* Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. Akira Hatanaka2011-08-162-5/+5
| | | | llvm-svn: 137706
* Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson2011-08-153-20/+27
| | | | | | Thumb2 NEON decoding hooks to bring us closer to correctness. llvm-svn: 137686
* While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG andBruno Cardoso Lopes2011-08-151-15/+25
| | | | | | also add the AVX versions of the 128-bit patterns llvm-svn: 137685
* Reorder declarations of vmovmskp* and also put the necessary AVXBruno Cardoso Lopes2011-08-151-31/+35
| | | | | | | predicate and TB encoding fields. This fix the encoding for the attached testcase. This fixes PR10625. llvm-svn: 137684
* MCTargetAsmParser target match predicate support.Jim Grosbach2011-08-153-2/+5
| | | | | | | | Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. llvm-svn: 137675
* Fix PR10656. It's only profitable to use 128-bit inserts and extractsBruno Cardoso Lopes2011-08-151-4/+6
| | | | | | | when AVX mode is one. Otherwise is just more work for the type legalizer. llvm-svn: 137661
* Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ↵Owen Anderson2011-08-151-0/+15
| | | | | | | | mode. Update tests to reflect this fact. Patch by James Molloy. llvm-svn: 137647
* Remove dead classes.Owen Anderson2011-08-151-33/+0
| | | | llvm-svn: 137643
* Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.Owen Anderson2011-08-151-2/+2
| | | | llvm-svn: 137641
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-6/+7
| | | | llvm-svn: 137636
* Fix problems decoding the to/from-lane NEON memory instructions, and add a ↵Owen Anderson2011-08-152-4/+486
| | | | | | comprehensive NEON decoding testcase. llvm-svn: 137635
* Update comment to reflect MC target machine refactor.Jim Grosbach2011-08-151-1/+1
| | | | llvm-svn: 137615
* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+46
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
* ARM STR_POST_IMM offset encoding fix in load/store optimizer.Jim Grosbach2011-08-121-13/+10
| | | | | | | | | Tidy up the code a bit and push the definition of the value next to the uses to try to minimize this sort of issue from arising again while I'm at it. rdar://9945172 llvm-svn: 137525
* Fix comment!Bruno Cardoso Lopes2011-08-121-3/+3
| | | | llvm-svn: 137521
* The VPERM2F128 is a AVX instruction which permutes between two 256-bitBruno Cardoso Lopes2011-08-127-0/+132
| | | | | | | | vectors. It operates on 128-bit elements instead of regular scalar types. Recognize shuffles that are suitable for VPERM2F128 and teach the x86 legalizer how to handle them. llvm-svn: 137519
* Move code around and add commentsBruno Cardoso Lopes2011-08-121-11/+13
| | | | llvm-svn: 137518
* Define unaligned load and store. Akira Hatanaka2011-08-124-2/+35
| | | | llvm-svn: 137515
* ARM expansion of pre-indexed store pseudos should maintain memoperands.Jim Grosbach2011-08-121-1/+3
| | | | | | Partial fix for rdar://9945172. llvm-svn: 137513
* Fix some remaining issues with decoding ARM-mode memory instructions, and ↵Owen Anderson2011-08-122-20/+12
| | | | | | add another batch of tests. llvm-svn: 137502
* Fix decoding of ARM-mode STRH.Owen Anderson2011-08-123-0/+6
| | | | llvm-svn: 137499
* Specify fixed bit in the LDRBT encoding, which allows us to distinguish it ↵Owen Anderson2011-08-121-1/+3
| | | | | | from certain USAT16 encodings. llvm-svn: 137494
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-122-0/+43
| | | | llvm-svn: 137487
* When constant double 0.0 is lowered, make sure 0 is copied directly from an Akira Hatanaka2011-08-121-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | integer register to a floating point register. It is not valid to interpret the value of a floating pointer register as part of a double precision floating point value after a single precision floating point computational or move instruction stores its result to the register. - In the test case, the following code is generated before this patch is applied: mtc1 $zero, $f2 ; unformatted copy to $f2 mov.s $f0, $f2 ; $f0 is in single format sdc1 $f12, 0($sp) mov.s $f1, $f2 ; $f1 is in single format c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double - The following code is generated after this patch is applied: mtc1 $zero, $f0 ; unformatted copy to $f0 mtc1 $zero, $f1 ; unformatted copy to $f1 c.eq.d $f12, $f0 ; $f0 can be interpreted as double Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and provided the test case. llvm-svn: 137484
* switch to the new struct apis.Chris Lattner2011-08-122-5/+5
| | | | llvm-svn: 137481
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-126-6/+9
| | | | | | when building with assertions disabled. llvm-svn: 137460
* findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.Andrew Trick2011-08-121-2/+2
| | | | | | Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it. llvm-svn: 137404
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Enclose directive .cprestore with .set macro and nomacro to silence assemblerAkira Hatanaka2011-08-111-3/+9
| | | | | | warning. llvm-svn: 137378
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Add a dag combine to xform 256-bit shuffles into simple vectorBruno Cardoso Lopes2011-08-111-1/+54
| | | | | | | inserts and extracts. This simple combine makes us generate only 1 instruction instead of 11 in the v8 case. llvm-svn: 137362
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Add isIndirectBranch flag.Akira Hatanaka2011-08-111-1/+2
| | | | llvm-svn: 137351
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
OpenPOWER on IntegriCloud