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* Add const.Rafael Espindola2014-03-284-7/+8
| | | | llvm-svn: 205013
* Revert "InstCombine: merge constants in both operands of icmp."Erik Verbruggen2014-03-281-0/+12
| | | | | | | | | This reverts commit r204912, and follow-up commit r204948. This introduced a performance regression, and the fix is not completely clear yet. llvm-svn: 205010
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-2815-85/+410
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* R600: avoid calling std::next on an iterator that might be end()Tim Northover2014-03-281-3/+3
| | | | | | | | This was causing my llc to go into an infinite loop on CodeGen/R600/address-space.ll (just triggered recently by some allocator changes). llvm-svn: 205005
* [PowerPC] Use a small cleanup pass to remove VSX self copiesHal Finkel2014-03-273-0/+78
| | | | | | | | | | | | As explained in r204976, because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) This adds a small cleanup pass to remove these prior to post-RA scheduling. llvm-svn: 204980
* Canonicalise Windows target triple spellingsSaleem Abdulrasool2014-03-272-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Construct a uniform Windows target triple nomenclature which is congruent to the Linux counterpart. The old triples are normalised to the new canonical form. This cleans up the long-standing issue of odd naming for various Windows environments. There are four different environments on Windows: MSVC: The MS ABI, MSVCRT environment as defined by Microsoft GNU: The MinGW32/MinGW32-W64 environment which uses MSVCRT and auxiliary libraries Itanium: The MSVCRT environment + libc++ built with Itanium ABI Cygnus: The Cygwin environment which uses custom libraries for everything The following spellings are now written as: i686-pc-win32 => i686-pc-windows-msvc i686-pc-mingw32 => i686-pc-windows-gnu i686-pc-cygwin => i686-pc-windows-cygnus This should be sufficiently flexible to allow us to target other windows environments in the future as necessary. llvm-svn: 204977
* [PowerPC] Don't remove self VSX copies in PPCInstrInfo::copyPhysRegHal Finkel2014-03-271-9/+13
| | | | | | | | | | | | | | | Because of how the allocation of VSX registers interacts with the call-lowering code, we sometimes end up generating self VSX copies. Specifically, things like this: %VSL2<def> = COPY %F2, %VSL2<imp-use,kill> (where %F2 is really a sub-register of %VSL2, and so this copy is a nop) The problem is that ExpandPostRAPseudos always assumes that *some* instruction has been inserted, and adds implicit defs to it. This is a problem if no copy was inserted because it can cause subtle problems during post-RA scheduling. These self copies will have to be removed some other way. llvm-svn: 204976
* [X86][Vector Cost Model] Add a comment to explain the workaroundQuentin Colombet2014-03-271-0/+5
| | | | | | | | in my previous commit (r204884). <rdar://problem/16381225> llvm-svn: 204972
* [PowerPC] Fix v2f64 vector extract and related patternsHal Finkel2014-03-272-4/+4
| | | | | | | | | First, v2f64 vector extract had not been declared legal (and so the existing patterns were not being used). Second, the patterns for that, and for scalar_to_vector, should really be a regclass copy, not a subregister operation, because the VSX registers directly hold both the vector and scalar data. llvm-svn: 204971
* [PowerPC] Expand v2i64 shiftsHal Finkel2014-03-271-0/+4
| | | | | | | | These operations need to be expanded during legalization so that isel does not crash. In theory, we might be able to custom lower some of these. That, however, would need to be follow-up work. llvm-svn: 204963
* Remove another unused argument.Rafael Espindola2014-03-278-22/+17
| | | | llvm-svn: 204961
* Remove unused argument.Rafael Espindola2014-03-278-40/+23
| | | | llvm-svn: 204956
* R600: Implement isZExtFree.Matt Arsenault2014-03-272-0/+20
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-274-4/+28
| | | | llvm-svn: 204945
* [mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR'sDaniel Sanders2014-03-276-23/+23
| | | | | | | | | | | | Summary: No functional change since these predicates are (currently) synonymous. Extracted from a patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3202 llvm-svn: 204943
* [AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTSLogan Chien2014-03-272-0/+91
| | | | | | | | Lower SHL_PARTS, SRA_PARTS and SRL_PARTS to perform 128-bit integer shift Patch by GuanHong Liu. llvm-svn: 204940
* Prevent alias from pointing to weak aliases.Rafael Espindola2014-03-277-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds back r204781. Original message: Aliases are just another name for a position in a file. As such, the regular symbol resolutions are not applied. For example, given define void @my_func() { ret void } @my_alias = alias weak void ()* @my_func @my_alias2 = alias void ()* @my_alias We produce without this patch: .weak my_alias my_alias = my_func .globl my_alias2 my_alias2 = my_alias That is, in the resulting ELF file my_alias, my_func and my_alias are just 3 names pointing to offset 0 of .text. That is *not* the semantics of IR linking. For example, linking in a @my_alias = alias void ()* @other_func would require the strong my_alias to override the weak one and my_alias2 would end up pointing to other_func. There is no way to represent that with aliases being just another name, so the best solution seems to be to just disallow it, converting a miscompile into an error. llvm-svn: 204934
* [mips] Attempting to use register $32 should be an error instead of an ↵Daniel Sanders2014-03-271-1/+1
| | | | | | | | | | | | assertion. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3201 llvm-svn: 204932
* The forward declare should be a struct instead of a class (to be consistent ↵Aaron Ballman2014-03-271-1/+1
| | | | | | with the definition, as well as to silence an MSVC C4099 warning). llvm-svn: 204928
* [mips] Add support for .cpsetupDaniel Sanders2014-03-271-0/+133
| | | | | | | | | | | | | | Summary: Patch by Robert N. M. Watson His work was sponsored by: DARPA, AFRL Small corrections by myself. CC: theraven, matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3199 llvm-svn: 204924
* [mips] The decision between GOT_DISP and GOT16 for global addresses depends ↵Daniel Sanders2014-03-271-2/+2
| | | | | | | | | | | | | | on ABI rather than MIPS64 Summary: No functional change (for supported use cases) Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3191 llvm-svn: 204922
* Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and ↵Zoran Jovanovic2014-03-272-195/+241
| | | | | | | | Split the file MipsAsmBackend.h. Differential Revision: http://llvm-reviews.chandlerc.com/D3134 llvm-svn: 204921
* [mips] Remove unused private field.Matheus Almeida2014-03-271-2/+1
| | | | llvm-svn: 204919
* [mips] NaCl should now use the custom MipsELFStreamer (recently added) in spiteMatheus Almeida2014-03-273-14/+18
| | | | | | | | | | | | | | of MCELFStreamer. This is so that changes to MipsELFStreamer will automatically propagate through its subclasses. No functional changes (MipsELFStreamer has the same functionality of MCELFStreamer at the moment). Differential Revision: http://llvm-reviews.chandlerc.com/D3130 llvm-svn: 204918
* [mips] Implement custom MCELFStreamer.Matheus Almeida2014-03-274-1/+66
| | | | | | | | | | | | | This allows us to insert some hooks before emitting data into an actual object file. For example, we can capture the register usage for a translation unit by overriding the EmitInstruction method. The register usage information is needed to generate .reginfo and .Mips.options ELF sections. No functional changes. Differential Revision: http://llvm-reviews.chandlerc.com/D3129 llvm-svn: 204917
* InstCombine: merge constants in both operands of icmp.Erik Verbruggen2014-03-271-12/+0
| | | | | | | | | | Transform: icmp X+Cst2, Cst into: icmp X, Cst-Cst2 when Cst-Cst2 does not overflow, and the add has nsw. llvm-svn: 204912
* [mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and ↵Daniel Sanders2014-03-273-55/+53
| | | | | | | | | | | | | | | | | | | isABI_N64() from MipsSubTarget in MipsTargetLowering Summary: The short name is quite convenient so provide an accessor for them instead. No functional change Depends on D3177 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3178 llvm-svn: 204911
* AVX-512: Implemented masking for integer arithmetic & logic instructions.Elena Demikhovsky2014-03-272-94/+276
| | | | | | By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
* Rejected r204899 and r204900 due to remaining test failures on ↵Stepan Dyatkovskiy2014-03-271-17/+1
| | | | | | cmake-llvm-x86_64-linux buildbot. llvm-svn: 204901
* Fix for pr18931: Crash using integrated assembler with immediate arithmeticStepan Dyatkovskiy2014-03-271-1/+17
| | | | | | | | | | | Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 204899
* ARM: raise error message when complex SO expressions can't really beJiangning Liu2014-03-271-1/+1
| | | | | | solved as a constant at compilation time. llvm-svn: 204898
* [X86][Vectorizer Cost Model] Correct vectorization cost model for v2i64->v2f64Quentin Colombet2014-03-271-0/+2
| | | | | | | | | | and v4i64->v4f64. The new costs match what we did for SSE2 and reflect the reality of our codegen. <rdar://problem/16381225> llvm-svn: 204884
* X86: Correct vectorization cost model for v8f32->v8i8.Jim Grosbach2014-03-271-1/+1
| | | | | | | | Fix the cost model to reflect the reality of our codegen. rdar://16370633 llvm-svn: 204880
* [PowerPC] Generate VSX permutations for v2[fi]64 vectorsHal Finkel2014-03-263-5/+45
| | | | llvm-svn: 204873
* Fix a problem with the ARM assembler incorrectly matching aKevin Enderby2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector list parameter that is using all lanes "{d0[], d2[]}" but can match and instruction with a ”{d0, d2}" parameter. I’m finishing up a fix for proper checking of the unsupported alignments on vld/vst instructions and ran into this. Thus I don’t have a test case at this time. And adding all code that will demonstrate the bug would obscure the very simple one line fix. So if you would indulge me on not having a test case at this time I’ll instead offer up a detailed explanation of what is going on in this commit message. This instruction: vld2.8 {d0[], d2[]}, [r4:64] is not legal as the alignment can only be 16 when the size is 8. Per this documentation: A8.8.325 VLD2 (single 2-element structure to all lanes) <align> The alignment. It can be one of: 16 2-byte alignment, available only if <size> is 8, encoded as a = 1. 32 4-byte alignment, available only if <size> is 16, encoded as a = 1. 64 8-byte alignment, available only if <size> is 32, encoded as a = 1. omitted Standard alignment, see Unaligned data access on page A3-108. So when code is added to the llvm integrated assembler to not match that instruction because of the alignment it then goes on to try to match other instructions and comes across this: vld2.8 {d0, d2}, [r4:64] and and matches it. This is because of the method ARMOperand::isVecListDPairSpaced() is missing the check of the Kind. In this case the Kind is k_VectorListAllLanes . While the name of the method may suggest that this is OK it really should check that the Kind is k_VectorList. As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was used to match {d0[], d2[]} and correctly checks the Kind: bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } where the original ARMOperand::isVecListDPairSpaced() does not check the Kind: bool isVecListDPairSpaced() const { if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } Jim Grosbach has reviewed the change and said: Yep, that sounds right. … And by "right" I mean, "wow, that's a nasty latent bug I'm really, really glad to see fixed." :) rdar://16436683 llvm-svn: 204861
* [PowerPC] VSX loads and stores support unaligned accessHal Finkel2014-03-262-3/+10
| | | | | | | I've not yet updated PPCTTI because I'm not sure what the actual relative cost is compared to the aligned uses. llvm-svn: 204848
* Fix the ARM VST4 (single 4-element structure from one lane)Kevin Enderby2014-03-261-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! was being printed as: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! rdar://16435096 llvm-svn: 204847
* [PowerPC] Use v2f64 <-> v2i64 VSX conversion instructionsHal Finkel2014-03-262-4/+13
| | | | llvm-svn: 204843
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* [PowerPC] Remove some dead VSX v4f32 store patternsHal Finkel2014-03-261-4/+2
| | | | | | | | | These patterns are dead (because v4f32 stores are currently promoted to v4i32 and stored using Altivec instructions), and also are likely not correct (because they'd store the vector elements in the opposite order from that assumed by the rest of the Altivec code). llvm-svn: 204839
* [PowerPC] Use VSX vector load/stores for v2[fi]64Hal Finkel2014-03-262-0/+13
| | | | | | | | These instructions have access to the complete VSX register file. In addition, they "swap" the order of the elements so that element 0 (the scalar part) comes first in memory and element 1 follows at a higher address. llvm-svn: 204838
* Revert "X86 memcpy lowering: use "rep movs" even when esi is used as base ↵Hans Wennborg2014-03-261-29/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | pointer" (r204174) > For functions where esi is used as base pointer, we would previously fall ba > from lowering memcpy with "rep movs" because that clobbers esi. > > With this patch, we just store esi in another physical register, and restore > it afterwards. This adds a little bit of register preassure, but the more > efficient memcpy should be worth it. > > Differential Revision: http://llvm-reviews.chandlerc.com/D2968 This didn't work. I was ending up with code like this: lea edi,[esi+38h] mov ecx,0Fh mov edx,esi mov esi,ebx rep movs dword ptr es:[edi],dword ptr [esi] lea ecx,[esi+74h] <-- Ooops, we're now using esi before restoring it from edx. add ebx,3Ch mov esi,edx I guess if we want to do this we need stronger glue or something, or doing the expansion much later. llvm-svn: 204829
* [PowerPC] Add v2i64 as a legal VSX typeHal Finkel2014-03-264-9/+32
| | | | | | | | | v2i64 needs to be a legal VSX type because it is the SetCC result type from v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations. This fixes the lowering for v2f64 VSELECT. llvm-svn: 204828
* [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.Matheus Almeida2014-03-262-24/+1
| | | | | | | | This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
* [mips] Add support to the '.dword' directive.Matheus Almeida2014-03-261-0/+5
| | | | | | | The '.dword' directive accepts a list of expressions and emits them in 8-byte chunks in successive locations. llvm-svn: 204822
* [mips] Rename function in MipsAsmParser.Matheus Almeida2014-03-261-4/+4
| | | | | | | | | | | | parseDirectiveWord is a generic function that parses an expression which means there's no need for it to have such an specific name. Renaming it to parseDataDirective so that it can also be used to handle .dword directives[1]. [1]To be added in a follow up commit. No functional changes. llvm-svn: 204818
* [mips] Add support to '.set mips64'.Matheus Almeida2014-03-263-0/+17
| | | | | | | | | | The '.set mips64' directive enables the feature Mips:FeatureMips64 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204817
* [mips] Add support to '.set mips64r2'.Matheus Almeida2014-03-263-0/+17
| | | | | | | | | | The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64r2 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204815
* AArch64_BE function argument passing for ARM ABIChristian Pirker2014-03-261-2/+11
| | | | llvm-svn: 204814
* ARM: add intrinsics for the v8 ldaex/stlexTim Northover2014-03-264-26/+98
| | | | | | | | | We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
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