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* Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach2011-12-051-0/+20
| | | | | | rdar://10529664 llvm-svn: 145860
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-052-12/+17
| | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
* Split ExtIns into two base classes and have instructions EXT and INS derive fromAkira Hatanaka2011-12-051-17/+21
| | | | | | them. llvm-svn: 145852
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-051-0/+18
| | | | | | rdar://10529348 llvm-svn: 145851
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-051-20/+16
| | | | | | O32 with relocation-model=pic too. llvm-svn: 145850
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-052-10/+74
| | | | | | Finish up rdar://10522016. llvm-svn: 145846
* Fix previous commit. Oops.Jim Grosbach2011-12-051-3/+3
| | | | llvm-svn: 145844
* Tidy up. No functional change.Jim Grosbach2011-12-051-9/+6
| | | | llvm-svn: 145843
* ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach2011-12-052-0/+11
| | | | | | | | | Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 llvm-svn: 145842
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-053-17/+13
| | | | llvm-svn: 145819
* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
| | | | llvm-svn: 145818
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
| | | | llvm-svn: 145816
* Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR ↵Craig Topper2011-12-051-2/+2
| | | | | | instructions. llvm-svn: 145804
* Clean up and optimizations to the X86 shuffle lowering code. No functional ↵Craig Topper2011-12-051-52/+36
| | | | | | change. llvm-svn: 145803
* Fix 80-column issues.Bob Wilson2011-12-041-4/+8
| | | | llvm-svn: 145783
* Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov2011-12-031-0/+1
| | | | | | | | Maybe some targets should use this as well. Patch by Evgeniy Stepanov! llvm-svn: 145781
* Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() sinceVenkatraman Govindaraju2011-12-031-1/+1
| | | | | | AnalyzeBranch doesn't change the successor, just the order. llvm-svn: 145779
* Check for stack space more intelligently.Sanjoy Das2011-12-031-4/+16
| | | | | | | | | libgcc sets the stack limit field in TCB to 256 bytes above the actual allocated stack limit. This means if the function's stack frame needs less than 256 bytes, we can just compare the stack pointer with the stack limit. This should result in lesser calls to __morestack. llvm-svn: 145766
* Fix a bug in the x86-32 code generated for segmented stacks.Sanjoy Das2011-12-031-8/+0
| | | | | | | | | | Currently LLVM pads the call to __morestack with a add and sub of 8 bytes to esp. This isn't correct since __morestack expects the call to be followed directly by a ret. This commit also adjusts the relevant test-case. llvm-svn: 145765
* Creating multiple JITs on X86 in multiple threads causes multiple writes (ofNick Lewycky2011-12-031-0/+2
| | | | | | | | the same value) to this variable. This code could be refactored, but it doesn't matter since the old JIT is going away. Add tsan annotations to ignore the race. llvm-svn: 145745
* [arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier2011-12-031-3/+18
| | | | | | rdar://10510150 llvm-svn: 145742
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-023-11/+56
| | | | llvm-svn: 145726
* ARM VEXT tighten up operand classes a bit.Jim Grosbach2011-12-021-2/+2
| | | | llvm-svn: 145722
* ARM VST1 single lane assembly parsing.Jim Grosbach2011-12-022-4/+179
| | | | llvm-svn: 145718
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-0243-373/+264
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* ARM VLD1 single lane assembly parsing.Jim Grosbach2011-12-023-9/+124
| | | | llvm-svn: 145712
* ARM encoder method needs the physical register number, not the enum.Jim Grosbach2011-12-021-1/+1
| | | | llvm-svn: 145711
* [arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier2011-12-021-2/+4
| | | | | | | | argument value type. Otherwise, the sign/zero-extend has no effect on arguments passed via the stack (i.e., undefined high-order bits). rdar://10515467 llvm-svn: 145701
* Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach2011-12-023-26/+133
| | | | | | Add the 16-bit lane variants while I'm at it. llvm-svn: 145693
* Add XOP feature flag.Jan Sjödin2011-12-023-2/+12
| | | | llvm-svn: 145682
* Reduce duplicate code in isHorizontalBinOp and add some asserts to protect ↵Craig Topper2011-12-021-32/+24
| | | | | | assumptions llvm-svn: 145681
* Add instruction selection support for horizontal add/sub of 256-bit floating ↵Craig Topper2011-12-021-2/+4
| | | | | | point vectors. Also add the test case for 256-bit integer vectors. llvm-svn: 145680
* remove unneeded FIXME commentHal Finkel2011-12-021-1/+0
| | | | llvm-svn: 145679
* update PPC 940 hazard rec. to function in postRA modeHal Finkel2011-12-026-142/+93
| | | | llvm-svn: 145676
* ARM start parsing VLD1 single lane instructions.Jim Grosbach2011-12-022-14/+115
| | | | | | | The alias pseudos need cleaned up for size suffix handling, but this gets the basics working. Will be cleaning up and adding more. llvm-svn: 145655
* Dummy commit to check commit access.Sanjoy Das2011-12-011-1/+1
| | | | llvm-svn: 145619
* Add missing functions.Chad Rosier2011-12-011-1/+4
| | | | llvm-svn: 145608
* Add a few more functions to TargetLibraryInfo. More of rdar://10500969.Chad Rosier2011-12-011-1/+16
| | | | llvm-svn: 145596
* For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher2011-12-011-1/+17
| | | | | | | | sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 llvm-svn: 145579
* Pass AVX vectors which are arguments to varargs functions on the stack. ↵Eli Friedman2011-12-011-4/+9
| | | | | | <rdar://problem/10463281>. llvm-svn: 145573
* Small fix for assembler generation on Darwin PPC64. Patch by Michael ↵Eli Friedman2011-12-011-1/+1
| | | | | | Kostylev. PR11437. llvm-svn: 145553
* Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin2011-11-301-0/+349
| | | | | | remaining FMA4 instructions and intrinsics with tests. llvm-svn: 145525
* Remove unused variableMatt Beaumont-Gay2011-11-301-2/+0
| | | | llvm-svn: 145517
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-304-43/+82
| | | | llvm-svn: 145510
* Add a few functions to TargetLibraryInfo.Chad Rosier2011-11-301-2/+50
| | | | llvm-svn: 145508
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-305-5/+30
| | | | llvm-svn: 145504
* X86: Turns out bulldozer also supports sse42 and lzcnt.Benjamin Kramer2011-11-301-11/+6
| | | | | | | While at it remove the barcelona/instanbul/shanghai subtargets, they're unsupported by GCC and look pretty broken. llvm-svn: 145494
* X86: Add subtargets for AMD's bulldozer.Benjamin Kramer2011-11-301-0/+6
| | | | llvm-svn: 145493
* X86: PerformOrCombine introduced a vselect node with a wrong order of ↵Nadav Rotem2011-11-301-1/+1
| | | | | | operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). llvm-svn: 145488
* Add instruction selection support for AVX2 horizontal add/sub instructions.Craig Topper2011-11-301-24/+49
| | | | llvm-svn: 145487
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