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* [X86] Tidyup subvector insert/extract helpers. NFCI.Simon Pilgrim2017-05-021-24/+9
| | | | | | Use getConstantOperandVal where possible. llvm-svn: 301912
* Fix typo in comment. NFCI.Simon Pilgrim2017-05-021-2/+2
| | | | llvm-svn: 301911
* [ARM] GlobalISel: Use TableGen instruction selectorDiana Picus2017-05-025-22/+57
| | | | | | | | | | | Emit and use the TableGen instruction selector for ARM. At the moment, this allows us to remove the hand-written code for selecting G_SDIV and G_UDIV. Future commits will focus on increasing the code coverage for it and removing more dead code from the current instruction selector. llvm-svn: 301905
* [AVR] Save/restore the frame pointer for all functionsDylan McKay2017-05-021-11/+10
| | | | | | | A recent commit I made made it so that we only did this for signal or interrupt handlers. This broke normal functions. llvm-svn: 301893
* [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LENemanja Ivanovic2017-05-022-6/+23
| | | | | | | | | | | | | Fixes PR30730. This is a re-commit of a pulled commit. The commit was pulled because some software projects contained uses of Altivec vectors that violated alignment requirements. Known issues have now been fixed. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D26861 llvm-svn: 301892
* [AVR] Fix a bug where the frame pointer is clobberedDylan McKay2017-05-021-7/+17
| | | | | | | | | | | | | | | Because it was a callee-saved register, we automatically generated code to spill and unspill its original value so that it is restored after the function returns. The problem is that this code was being generated before the epilogue. The epilogue itself uses the Y register, which could be prematurely restored by the CSR restoration process. This removes R29R28 from the CSR list and changes the prologue/epilogue code to handle it explicitly. llvm-svn: 301887
* [AVR] Enable the frame pointer for all functionsDylan McKay2017-05-011-2/+3
| | | | | | | This is a temporary measure while we figure out a way to get the frame pointer working correctly. llvm-svn: 301881
* [X86] Reduce code for setting operations actions by merging into loops ↵Simon Pilgrim2017-05-011-129/+68
| | | | | | across multiple types/ops. NFCI. llvm-svn: 301879
* [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-05-012-56/+64
| | | | | | NFC llvm-svn: 301841
* [X86][AVX] Rename LowerVectorBroadcast to lowerBuildVectorAsBroadcast. NFCI.Simon Pilgrim2017-05-011-11/+8
| | | | | | Since the shuffle refactor, this is only used during BUILD_VECTOR lowering. llvm-svn: 301834
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-0110-114/+187
| | | | | | | | A .cur instruction can be identified by checking isCVINew() && mayLoad(). Patch by Colin LeMahieu. llvm-svn: 301829
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-013-8/+23
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-7/+11
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* [Hexagon] Improve shuffle error reportingKrzysztof Parzyszek2017-05-0111-482/+276
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301823
* X86: initialize a few subtarget variables.Tim Northover2017-05-011-0/+3
| | | | | | Otherwise an indeterminate value gets read, causing a bunch of UBSan failures. llvm-svn: 301819
* Rename WeakVH to WeakTrackingVH; NFCSanjoy Das2017-05-012-14/+14
| | | | | | This relands r301424. llvm-svn: 301812
* [WebAssembly] Fix use of SDNodeFlags after API change in r301803Derek Schuff2017-05-011-2/+2
| | | | llvm-svn: 301811
* Remove unnecessary conditions as suggested by clang-tidy. NFCGabor Horvath2017-05-011-1/+1
| | | | | | | | Patch by: Gergely Angeli! Differential Revision: https://reviews.llvm.org/D31936 llvm-svn: 301807
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-016-34/+32
| | | | | | | | This removes BinaryWithFlagsSDNode, and flags are now all passed by value. Differential Revision: https://reviews.llvm.org/D32527 llvm-svn: 301803
* [AVR] Implement non-constant bit rotationsDylan McKay2017-05-013-1/+63
| | | | | | This lets us do bit rotations of variable amount. llvm-svn: 301794
* [GlobalISel][X86] Prioritize Tablegen-erated instruction selection. NFCIgor Breger2017-05-011-50/+8
| | | | | | | | | | | | | | | | Summary: Prioritizes Tablegen-erated instruction selection over C++ instruction selection. Remove G_ADD/G_SUB C++ selection - implemented by Tablegen. Reviewers: dsanders, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32677 llvm-svn: 301792
* [GlobalISel][X86] G_SEXT/G_ZEXT support.Igor Breger2017-05-011-0/+20
| | | | | | | | | | | | Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32591 llvm-svn: 301790
* [GlobalISel][X86] G_LOAD/G_STORE pointer selection support.Igor Breger2017-05-011-2/+2
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_LOAD/G_STORE pointer selection support. Reviewers: zvi, guyblank Reviewed By: zvi, guyblank Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32217 llvm-svn: 301788
* [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offsetDylan McKay2017-04-303-8/+9
| | | | | | | Before this, the LDS/STS instructions would have their opcodes overwritten while linking. llvm-svn: 301782
* Do not legalize large add with addc/adde, introduce addcarry and do it with ↵Amaury Sechet2017-04-302-0/+65
| | | | | | | | | | | | | | uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
* [APInt] Replace calls to setBits with more specific calls to setBitsFrom and ↵Craig Topper2017-04-301-3/+3
| | | | | | setLowBits where possible. llvm-svn: 301768
* [X86] Clear KnownBits instead of reconstructing it. NFCCraig Topper2017-04-301-1/+1
| | | | llvm-svn: 301767
* [mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of ↵Simon Atanasyan2017-04-304-1/+9
| | | | | | | | | | | microMIPS In case of microMIPS mode %gottprel operator should emit microMIPS relocation R_MICROMIPS_TLS_GOTTPREL, not R_MIPS_TLS_GOTTPREL. Differential Revision: http://reviews.llvm.org/D32617 llvm-svn: 301763
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-2910-44/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* [mips][FastISel] Fix a nullptr deference.Simon Dardis2017-04-291-1/+2
| | | | | | | r301392 introduced a potential nullptr deference causing compilation failures. llvm-svn: 301746
* AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault2017-04-291-4/+9
| | | | | | | | | This would assert when there were multiple defs of a physical register. We just need to move all of the users of it. llvm-svn: 301730
* Revert r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Hans Wennborg2017-04-281-4/+5
| | | | | | | | | | | | | | | | | | AttributeList" This broke the Clang build. (Clang-side patch missing?) Original commit message: > [IR] Make add/remove Attributes use AttrBuilder instead of > AttributeList > > This change cleans up call sites and avoids creating temporary > AttributeList objects. > > NFC llvm-svn: 301712
* [RDF] Correctly calculate lane masks for defsKrzysztof Parzyszek2017-04-281-2/+7
| | | | llvm-svn: 301700
* [Hexagon] Do not move a block if it is on a fall-through pathKrzysztof Parzyszek2017-04-281-3/+10
| | | | llvm-svn: 301698
* [IR] Make add/remove Attributes use AttrBuilder instead of AttributeListReid Kleckner2017-04-281-5/+4
| | | | | | | | | This change cleans up call sites and avoids creating temporary AttributeList objects. NFC llvm-svn: 301697
* Make getParamAlignment use argument numbersReid Kleckner2017-04-282-3/+3
| | | | | | | | | | | | | | | | | | The method is called "get *Param* Alignment", and is only used for return values exactly once, so it should take argument indices, not attribute indices. Avoids confusing code like: IsSwiftError = CS->paramHasAttr(ArgIdx, Attribute::SwiftError); Alignment = CS->getParamAlignment(ArgIdx + 1); Add getRetAlignment to handle the one case in Value.cpp that wants the return value alignment. This is a potentially breaking change for out-of-tree backends that do their own call lowering. llvm-svn: 301682
* TargetLowering: Add finalizeLowering() function; NFCMatthias Braun2017-04-282-8/+14
| | | | | | | | | | | | | | | | | Adds a new method finalizeLowering to TargetLoweringBase. This is in preparation for an upcoming commit. This function is meant for target specific adjustments to MachineFrameInfo or register reservations. Move the freezeRegisters() and the hasCopyImplyingStackAdjustment() handling into the new function to prove the concept. As an added bonus GlobalISel no longer missed the hasCopyImplyingStackAdjustment() handling with this. Differential Revision: https://reviews.llvm.org/D32621 llvm-svn: 301679
* AMDGPU: Add new amdgcn.init.exec intrinsicsMarek Olsak2017-04-285-0/+101
| | | | | | | | | | v2: More tests, bug fixes, cosmetic changes. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D31762 llvm-svn: 301677
* Kill off the old SimplifyInstruction API by converting remaining users.Daniel Berlin2017-04-281-3/+3
| | | | llvm-svn: 301673
* Use Argument::hasAttribute and AttributeList::ReturnIndex moreReid Kleckner2017-04-285-52/+38
| | | | | | | | | | | This eliminates many extra 'Idx' induction variables in loops over arguments in CodeGen/ and Target/. It also reduces the number of places where we assume that ReturnIndex is 0 and that we should add one to argument numbers to get the corresponding attribute list index. NFC llvm-svn: 301666
* Clean up DIExpression::prependDIExpr a little. (NFC)Adrian Prantl2017-04-281-4/+3
| | | | llvm-svn: 301662
* [bpf] add bigendian support to disassemblerAlexei Starovoitov2017-04-281-7/+19
| | | | | | | | | . swap 4-bit register encoding, 16-bit offset and 32-bit imm to support big endian archs . add a test Reported-by: David S. Miller <davem@davemloft.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 301653
* Move variable local to where ita used. NFCI.Simon Pilgrim2017-04-281-1/+1
| | | | llvm-svn: 301646
* [ARM] GlobalISel: fixup r301632Diana Picus2017-04-281-42/+0
| | | | | | | Actually remove ARMInstructionSelector.h... Forgot to stage the removal in the previous commit. llvm-svn: 301633
* [ARM] GlobalISel: Get rid of ARMInstructionSelector.h. NFC.Diana Picus2017-04-283-3/+31
| | | | | | | | | Declare the ARMInstructionSelector in an anonymous namespace, to make it more in line with the other targets which were migrated to this in r299637 in order to avoid TableGen'erated headers being included in non-GlobalISel builds. llvm-svn: 301632
* [DebugInfo][X86] Improve X86 Optimize LEAs handling of debug values.Andrew Ng2017-04-281-7/+48
| | | | | | | | | | | | | | | This is a follow up to the fix in r298360 to improve the handling of debug values when redundant LEAs are removed. The fix in r298360 effectively discarded the debug values. This patch now attempts to preserve the debug values by using the DWARF DW_OP_stack_value operation via prependDIExpr. Moved functions appendOffset and prependDIExpr from Local.cpp to DebugInfoMetadata.cpp and made them available as static member functions of DIExpression. Differential Revision: https://reviews.llvm.org/D31604 llvm-svn: 301630
* [WebAssembly] Update calls to computeKnownBits after the changes from r301620.Craig Topper2017-04-282-5/+6
| | | | | | I didn't realize WebAssembly wasn't a default build target so I missed that changes were needed. llvm-svn: 301629
* [X86][NFC] Refactor RepMovsRepeats in preparation for D32481.Clement Courbet2017-04-281-49/+45
| | | | | | Differential Revision: https://reviews.llvm.org/D32583 llvm-svn: 301628
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and ↵Craig Topper2017-04-2821-208/+199
| | | | | | | | | | | | simplifyDemandedBits This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently. This is largely a mechanical transformation from KnownZero to Known.Zero. Differential Revision: https://reviews.llvm.org/D32569 llvm-svn: 301620
* [SelectionDAG] Use various APInt methods to reduce temporary APInt creationCraig Topper2017-04-281-1/+1
| | | | | | This patch uses various APInt methods to reduce the number of temporary APInts. These were all found while working through converting SelectionDAG's computeKnownBits to also use the KnownBits struct recently added to the ValueTracking version. llvm-svn: 301618
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