| Commit message (Collapse) | Author | Age | Files | Lines |
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Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
llvm-svn: 96556
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llvm-svn: 96540
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since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
llvm-svn: 96525
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A8.6.30
llvm-svn: 96523
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* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
llvm-svn: 96521
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B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
llvm-svn: 96519
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llvm-svn: 96504
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symbols could be emitted in the same file (it was uniqued by block number, but not by function number). " Patch by Nathan Keynes!
llvm-svn: 96495
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and add a sparc implementation that knows about delay slots. Patch by
Nathan Keynes!
llvm-svn: 96492
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llvm-svn: 96490
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cloned functions.
llvm-svn: 96485
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with mangled names).
llvm-svn: 96465
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Renamed PIC16FrameOverlay namespace to PIC16OVERLAY.
Renamed PIC16FrameOverlay class to PIC16Overlay.
llvm-svn: 96463
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A8.6.18 BFI - Bitfield insert (Encoding A1)
llvm-svn: 96462
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reverse engineering what they are.
llvm-svn: 96456
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Hopefully, this will fix the remaining issues seen there.
llvm-svn: 96454
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llvm-svn: 96440
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It's not clear why this is really required, but it was explicitly
added in r48808 with no real explanation or rdar #.
llvm-svn: 96438
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This pass is supposed to be run on the linked .bc module.
It traveses the module call graph twice. Once starting from the main function
and marking each reached function as "ML". Again, starting from the ISR
and cloning any reachable function that was marked as "ML". After cloning
the function, it remaps all the call sites in IL functions to call the
cloned functions.
Currently only marking is being done.
llvm-svn: 96435
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64 bits, fixing a variety of problems.
llvm-svn: 96421
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indentation. No functional changes.
llvm-svn: 96418
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llvm-svn: 96410
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into a roundss intrinsic, producing a cyclic dag. The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection. Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.
llvm-svn: 96408
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build failures due to my fix for pr6111.
llvm-svn: 96402
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llvm-svn: 96401
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llvm-svn: 96399
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llvm-svn: 96393
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If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).
Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335
llvm-svn: 96389
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llvm-svn: 96388
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non-temporal. Fix from r96241 for botched encoding of MOVNTDQ.
Add documentation for !nontemporal metadata.
Add a simpler movnt testcase.
llvm-svn: 96386
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to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
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set of Defs.
llvm-svn: 96383
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They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
llvm-svn: 96381
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o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
llvm-svn: 96380
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branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
llvm-svn: 96360
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methods to try to have the type predicates be more logically positioned.
llvm-svn: 96349
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and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
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llvm-svn: 96343
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llvm-svn: 96337
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not the end of the field, fixing rdar://7651978
llvm-svn: 96330
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Currently, whether a function is ISR or not is encoded in the section attribute for that function.
llvm-svn: 96322
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llvm-gcc but has been replaced with pad argument which don't need any
special backend support.
llvm-svn: 96312
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We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
llvm-svn: 96297
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llvm-svn: 96289
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llvm-svn: 96288
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llvm-svn: 96286
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Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
llvm-svn: 96285
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and the testcase needs improvement.
llvm-svn: 96265
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IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
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non-temporal.
llvm-svn: 96241
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