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* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-154-24/+20
| | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. llvm-svn: 108465
* fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,Chris Lattner2010-07-151-1/+1
| | | | | | | | this fixes rdar://8192860. Unfortunately it can only be triggered with llc because llvm-mc matches another (correctly encoded) version of this, so no testcase. llvm-svn: 108454
* Random note about bswap.Eli Friedman2010-07-151-0/+26
| | | | llvm-svn: 108396
* Last COPY conversion.Jakob Stoklund Olesen2010-07-141-3/+2
| | | | llvm-svn: 108387
* Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson2010-07-143-9/+4
| | | | | | | instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. llvm-svn: 108386
* Use TargetOpcode::COPY instead of X86-native register copy instructions whenJakob Stoklund Olesen2010-07-142-30/+27
| | | | | | | lowering atomics. This will allow those copies to still be coalesced after TII::isMoveInstr is removed. llvm-svn: 108385
* fix indentationChris Lattner2010-07-141-9/+7
| | | | llvm-svn: 108368
* Don't pass StringRef by reference.Benjamin Kramer2010-07-1424-41/+42
| | | | llvm-svn: 108366
* Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,Chris Lattner2010-07-142-100/+8
| | | | | | patch by Michael Spencer! llvm-svn: 108342
* Improve 64-subtraction of immediates when parts of the immediate can fitJim Grosbach2010-07-142-11/+40
| | | | | | | | | | | in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
* Add missing address register update to t2LDM_RET instruction.Bob Wilson2010-07-141-1/+1
| | | | | | Patch by Brian Lucas. PR7636. llvm-svn: 108332
* A couple potential optimizations inspired by comment 4 in PR6773.Eli Friedman2010-07-141-0/+41
| | | | llvm-svn: 108328
* Fix for PR7193 was overly conservative. The only case where sibcall calleeEvan Cheng2010-07-141-6/+12
| | | | | | | | | | address cannot be allocated a register is in 32-bit mode where the first three arguments are marked inreg. In that case EAX, EDX, and ECX will be used for argument passing. This fixes PR7610. llvm-svn: 108327
* Add support for NEON VMVN immediate instructions.Bob Wilson2010-07-143-7/+48
| | | | llvm-svn: 108324
* The bits in the cmode field of 32-bit VMOV immediate instructions all dependBob Wilson2010-07-141-2/+2
| | | | | | of the value of the immediate. llvm-svn: 108323
* fix a bug found by a warning I added to clang this morning.Chris Lattner2010-07-141-1/+1
| | | | llvm-svn: 108309
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+29
| | | | | | Radar 7373643. llvm-svn: 108303
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-1/+1
| | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. llvm-svn: 108302
* Add AVX 256-bit compare instructions and a bunch of testcasesBruno Cardoso Lopes2010-07-131-0/+10
| | | | llvm-svn: 108286
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-133-192/+78
| | | | | | NEON VMOV-immediate instructions. This simplifies some things. llvm-svn: 108275
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-134-15/+105
| | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. llvm-svn: 108274
* Added a check that pusha cannot be encoded in 64-bit mode.Kevin Enderby2010-07-131-0/+2
| | | | llvm-svn: 108265
* Extend the r107852 optimization which turns some fp compare to code sequence ↵Evan Cheng2010-07-133-71/+240
| | | | | | using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-132-1/+7
| | | | llvm-svn: 108256
* -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.Evan Cheng2010-07-131-1/+1
| | | | llvm-svn: 108254
* rotate CallInst operandsGabor Greif2010-07-131-5/+5
| | | | | | | | | | | | | | | | | with this commit the callee moves to the end of the operand array (from the start) and the call arguments now start at index 0 (formerly 1) this ordering is now consistent with InvokeInst this commit only flips the switch, functionally it is equivalent to r101465 I intend to commit several cleanups after a few days of soak period llvm-svn: 108240
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-134-77/+84
| | | | | | avoid replicated code. llvm-svn: 108227
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-12/+3
| | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. llvm-svn: 108226
* Add AVX 256-bit packed logical formsBruno Cardoso Lopes2010-07-131-0/+19
| | | | llvm-svn: 108224
* Add AVX 256-bit unop arithmetic instructionsBruno Cardoso Lopes2010-07-131-53/+86
| | | | llvm-svn: 108223
* Since AVX is a superset of all SSE versions, only use HasAVX for AVX ↵Bruno Cardoso Lopes2010-07-132-81/+77
| | | | | | instructions llvm-svn: 108222
* Move some SIMD fragment code into X86InstrFragmentsSIMD so that theDavid Greene2010-07-122-336/+336
| | | | | | | utility classes can be used from multiple files. This will aid transitioning to a new refactored x86 SIMD specification. llvm-svn: 108213
* Add AVX 256 binary arithmetic instructionsBruno Cardoso Lopes2010-07-121-7/+23
| | | | llvm-svn: 108207
* More refactoring of basic SSE arith instructions. Open room for 256-bit ↵Bruno Cardoso Lopes2010-07-121-207/+158
| | | | | | instructions llvm-svn: 108204
* Apply the SSE dependence idiom for SSE unary operations toDan Gohman2010-07-121-2/+8
| | | | | | | SD instructions too, in addition to SS instructions. And add a comment about it. llvm-svn: 108191
* Remove some code that doesn't appear to do anything. All the ARM callBob Wilson2010-07-121-5/+0
| | | | | | | | instructions already have implicit defs of LR. The comment suggests that this is intended to fix something like pr6111, but it doesn't really do that either. llvm-svn: 108186
* Add AVX 256-bit MOVMSK formsBruno Cardoso Lopes2010-07-121-0/+6
| | | | llvm-svn: 108184
* Check begin!=end, rather than !begin.Dan Gohman2010-07-121-2/+2
| | | | llvm-svn: 108167
* Don't fast-isel an x87 comparison opcode, as fast-isel doesn'tDan Gohman2010-07-121-2/+2
| | | | | | support branching on x87 comparisons yet. This fixes PR7624. llvm-svn: 108149
* Convert some tab stops into spaces.Duncan Sands2010-07-124-9/+9
| | | | llvm-svn: 108130
* Convert getLoadStoreRegOpcode to use a switch.Rafael Espindola2010-07-121-26/+29
| | | | llvm-svn: 108123
* Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola2010-07-121-21/+0
| | | | | | | | | | | | AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. llvm-svn: 108122
* A basic block that only uses RFP registers still needs the FP_REG_KILL marker.Jakob Stoklund Olesen2010-07-121-10/+7
| | | | | | This fixes PR7375. llvm-svn: 108120
* Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp toRafael Espindola2010-07-121-1/+2
| | | | | | | | | getMinimalPhysRegClass. It was used to produce spills, and it is better to use the most specific class if possible. Update getLoadStoreRegOpcode to handle GR32_AD. llvm-svn: 108115
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-1116-812/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Use target independent COPY instructions for the fake fextend and froundJakob Stoklund Olesen2010-07-111-6/+6
| | | | | | operations in x87 code. llvm-svn: 108098
* Remove redundant branch. Thanks, Anton!Jakob Stoklund Olesen2010-07-111-2/+0
| | | | llvm-svn: 108097
* Remove obsolete README_SSE note.Jakob Stoklund Olesen2010-07-111-10/+0
| | | | | | | | | | | | | | | We are generating movaps for all XMM register copies, including scalar floating point values. This is known to be at least as good as movss and movsd for all known architectures up to and including Nehalem because it avoids a partial register stall. The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when operands come from the integer unit). We don't now that switching movaps to movapd has any benefit. The same applies to andps -> pand. llvm-svn: 108096
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-114-40/+0
| | | | llvm-svn: 108094
* Replace copyRegToReg with copyPhysReg for SystemZ.Jakob Stoklund Olesen2010-07-112-58/+28
| | | | llvm-svn: 108092
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