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* MC: Clean up naming in MCObjectWriter. NFC.Jim Grosbach2015-06-0412-25/+25
| | | | | | | | | | | | | | | | | | | | s/WriteObject/writeObject/ s/RecordRelocation/recordRelocation/ s/IsSymbolRefDifferenceFullyResolved/isSymbolRefDifferenceFullyResolved/ s/Write8/write8/ s/WriteLE16/writeLE16/ s/WriteLE32/writeLE32/ s/WriteLE64/writeLE64/ s/WriteBE16/writeBE16/ s/WriteBE32/writeBE32/ s/WriteBE64/writeBE64/ s/Write16/write16/ s/Write32/write32/ s/Write64/write64/ s/WriteZeroes/writeZeroes/ s/WriteBytes/writeBytes/ llvm-svn: 239108
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-0415-2824/+58
| | | | llvm-svn: 239102
* [NVPTX] roll forward r239082Jingyue Wu2015-06-046-140/+179
| | | | | | | | | NVPTXISelDAGToDAG translates "addrspacecast to param" to NVPTX::nvvm_ptr_gen_to_param Added an llc test in bug21465. llvm-svn: 239100
* [Hexagon] Removing unused variable.Colin LeMahieu2015-06-041-1/+0
| | | | llvm-svn: 239097
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-0415-58/+2825
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* Revert r239082Jingyue Wu2015-06-045-175/+140
| | | | | | llc crashed for NVPTX backend llvm-svn: 239094
* [GlobalMerge] Take into account minsize on Global users' parents.Ahmed Bougacha2015-06-042-6/+13
| | | | | | | | | | Now that we can look at users, we can trivially do this: when we would have otherwise disabled GlobalMerge (currently -O<3), we can just run it for minsize functions, as it's usually a codesize win. Differential Revision: http://reviews.llvm.org/D10054 llvm-svn: 239087
* MC: Remove obsolete MachO UseAggressiveSymbolFolding.Jim Grosbach2015-06-044-12/+6
| | | | | | | | | | Fix the FIXME and remove this old as(1) compat option. It was useful for bringup of the integrated assembler to diff object files, but now it's just causing more relocations than strictly necessary to be generated. rdar://21201804 llvm-svn: 239084
* [NVPTX] kernel pointer arguments point to the global address spaceJingyue Wu2015-06-045-140/+175
| | | | | | | | | | | | | | | | | | | | | | | | Summary: With this patch, NVPTXLowerKernelArgs converts a kernel pointer argument to a pointer in the global address space. This change, along with NVPTXFavorNonGenericAddrSpaces, allows the NVPTX backend to emit ld.global.* and st.global.* for accessing kernel pointer arguments. Minor changes: 1. refactor: extract function convertToPointerInAddrSpace 2. fix a bug in the test case in bug21465.ll Test Plan: lower-kernel-ptr-arg.ll Reviewers: eliben, meheff, jholewinski Reviewed By: jholewinski Subscribers: wengxt, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10154 llvm-svn: 239082
* [bpf] add big- and host- endian supportAlexei Starovoitov2015-06-049-46/+130
| | | | | | | | | | | | | | | | | | | Summary: -march=bpf -> host endian -march=bpf_le -> little endian -match=bpf_be -> big endian Test Plan: v1 was tested by IBM s390 guys and appears to be working there. It bit rots too fast here. Reviewers: chandlerc, tstellarAMD Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10177 llvm-svn: 239071
* R600/SI: Reimplement isLegalAddressingModeMatt Arsenault2015-06-042-31/+70
| | | | | | | | | | | Now that we sometimes know the address space, this can theoretically do a better job. This needs better test coverage, but this mostly depends on first updating the loop optimizatiosn to provide the address space. llvm-svn: 239053
* R600/SI: Fix some cases for load / store of halfMatt Arsenault2015-06-042-3/+42
| | | | | | | Mostly argument loads were producing broken zextloads from an FP type. llvm-svn: 239049
* Replace custom fixed endian to raw_ostream emission with EndianStream.Benjamin Kramer2015-06-046-99/+28
| | | | | | Less code, clearer and more efficient. No functionality change intended. llvm-svn: 239040
* Replace string GNU Triples with llvm::Triple in MCAsmInfo subclasses and ↵Daniel Sanders2015-06-0431-65/+60
| | | | | | | | | | | | | | | | | | | | create*AsmInfo(). NFC. Summary: This is the first of several patches to eliminate StringRef forms of GNU triples from the internals of LLVM. After this is complete, GNU triples will be replaced by a more authoratitive representation in the form of an LLVM TargetTuple. Reviewers: rengolin Reviewed By: rengolin Subscribers: ted, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10236 llvm-svn: 239036
* AVX-512: I brought back vector-shuffle-512-v8.ll test.Elena Demikhovsky2015-06-041-1/+2
| | | | | | I re-generated it after all AVX-512 shuffle optimizations. llvm-svn: 239026
* AVX-512: added all SKX forms of VPERMW/D/Q instructions.Elena Demikhovsky2015-06-041-38/+50
| | | | | | | Added all forms of VPERMPS/PD instrcuctions. Added encoding tests. llvm-svn: 239016
* Removed {}, NFC.Elena Demikhovsky2015-06-041-2/+1
| | | | llvm-svn: 239014
* Bring back r239006 with a fix.Rafael Espindola2015-06-044-25/+10
| | | | | | | | | | | | | | | | | | | The fix is just that getOther had not been updated for packing the st_other values in fewer bits and could return spurious values: - unsigned Other = (getFlags() & (0x3f << ELF_STO_Shift)) >> ELF_STO_Shift; + unsigned Other = (getFlags() & (0x7 << ELF_STO_Shift)) >> ELF_STO_Shift; Original message: Pack the MCSymbolELF bit fields into MCSymbol's Flags. This reduces MCSymolfELF from 64 bytes to 56 bytes on x86_64. While at it, also make getOther/setOther easier to use by accepting unshifted STO_* values. llvm-svn: 239012
* Revert "Pack the MCSymbolELF bit fields into MCSymbol's Flags."Rafael Espindola2015-06-044-10/+25
| | | | | | | | This reverts commit r239006. I am debugging the powerpc failures. llvm-svn: 239010
* Pack the MCSymbolELF bit fields into MCSymbol's Flags.Rafael Espindola2015-06-044-25/+10
| | | | | | | | | This reduces MCSymolfELF from 64 bytes to 56 bytes on x86_64. While at it, also make getOther/setOther easier to use by accepting unshifted STO_* values. llvm-svn: 239006
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-047-54/+267
| | | | | | | | | | | | | | | | | | | | | | command-line options (3rd try) The first try (r238051) to land this was reverted due to ExecutionEngine build failure; that was hopefully addressed by r238788. The second try (r238842) to land this was reverted due to BUILD_SHARED_LIBS failure; that was hopefully addressed by r238953. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 239001
* R600: Re-enable sub-reg livenessTom Stellard2015-06-041-1/+1
| | | | | | The bug in the R600 backend that this uncovered has been fixed. llvm-svn: 238999
* Remove MCELFSymbolFlags.h. It is now internal to MCSymbolELF.Rafael Espindola2015-06-042-3/+1
| | | | llvm-svn: 238996
* Remove getOrCreateSymbolData. There is no MCSymbolData anymore.Rafael Espindola2015-06-033-3/+3
| | | | llvm-svn: 238952
* [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized ↵Colin LeMahieu2015-06-031-4/+0
| | | | | | variable issue was fixed. Removing re-registering ASM backend. llvm-svn: 238949
* [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test ↵Colin LeMahieu2015-06-033-28/+427
| | | | | | to make sure it is. llvm-svn: 238947
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-031-20/+22
| | | | | | | | | | | | | | | | The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 Recommiting after the revert in r238821, the buildbot still failed with the patch removed so there seems to be another reason for the breakage. llvm-svn: 238935
* [arm] Fix r238921. We must handle Constraint_i too.Daniel Sanders2015-06-031-0/+4
| | | | llvm-svn: 238925
* re-apply 238809Asaf Badouh2015-06-035-25/+107
| | | | | | | | | | AVX-512: Implemented GETEXP instruction for KNL and SKX Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. CR: http://reviews.llvm.org/D9991 llvm-svn: 238923
* [arm] Distinguish the /U[qytnms]/, 'Uv', 'Q', and 'm' inline assembly memory ↵Daniel Sanders2015-06-032-9/+44
| | | | | | | | | | | | | | | | | | | | | | constraints. Summary: But still handle them the same way since I don't know how they differ on this target. Of these, /U[qytnms]/ do not have backend tests but are accepted by clang. No functional change intended. Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D8203 llvm-svn: 238921
* AVX-512: More code improvements in shuffles, NFCElena Demikhovsky2015-06-031-21/+19
| | | | llvm-svn: 238919
* AVX-512: VSHUFPD instruction selection - code improvementsElena Demikhovsky2015-06-031-34/+36
| | | | llvm-svn: 238918
* AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions ↵Elena Demikhovsky2015-06-034-9/+61
| | | | | | | | | | for SKX and KNL. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238917
* X86: Added MPX feature and bound registers.Elena Demikhovsky2015-06-035-2/+18
| | | | | | | | | Intel® Memory Protection Extensions (Intel® MPX) is a new feature in Skylake. It is a part of KNL and SKX sets. It is also a part of Skylake client. I added definition of %bnd0 - %bnd3 registers, each register is a pair of 64-bit integers. llvm-svn: 238916
* [X86] Removed (unused) FSRL x86 operationSimon Pilgrim2015-06-034-21/+3
| | | | | | | | | | This patch removes the old X86ISD::FSRL op - which allowed float vectors to use the byte right shift operations (causing a domain switch....). Since the refactoring of the shuffle lowering code this no longer has any use. Differential Revision: http://reviews.llvm.org/D10169 llvm-svn: 238906
* Revert "make reciprocal estimate code generation more flexible by adding ↵Rafael Espindola2015-06-037-267/+54
| | | | | | | | | | command-line options (2nd try)" This reverts commit r238842. It broke -DBUILD_SHARED_LIBS=ON build. llvm-svn: 238900
* Avoid a call to getOrCreateSymbol when we already have the symbol.Rafael Espindola2015-06-031-2/+5
| | | | llvm-svn: 238890
* Pass a MCSymbolELF to a few ELF only functions. NFC.Rafael Espindola2015-06-021-1/+1
| | | | llvm-svn: 238868
* Merge MCELF.h into MCSymbolELF.h.Rafael Espindola2015-06-0213-63/+62
| | | | | | | Now that we have a dedicated type for ELF symbol, these helper functions can become member function of MCSymbolELF. llvm-svn: 238864
* AArch64: fix typo in SMIN far atomics and add testsTim Northover2015-06-021-1/+1
| | | | llvm-svn: 238858
* Push constness through LoopInfo::isLoopHeader and clean it up a bit.Benjamin Kramer2015-06-021-2/+1
| | | | | | NFC. llvm-svn: 238843
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-027-54/+267
| | | | | | | | | | | | | | | | | | | command-line options (2nd try) The first try (r238051) to land this was reverted due to bot failures that were hopefully addressed by r238788. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238842
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+7
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Shorten implementation of lowerV16X32VectorShuffle()Elena Demikhovsky2015-06-021-39/+61
| | | | | | | using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines. Added matching of VALIGN instruction. llvm-svn: 238830
* [mips] Add support for dynamic stack realignment.Vasileios Kalintiris2015-06-028-8/+141
| | | | | | | | | | | | | | | | | | | | Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 llvm-svn: 238829
* Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin2015-06-021-22/+20
| | | | | | | | | This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. llvm-svn: 238821
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-028-5/+432
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-023-0/+48
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-021-14/+51
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-025-107/+25
| | | | llvm-svn: 238810
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