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* Follow-up for r217020: actually commit the fix for PR20800,Alexander Potapenko2014-09-031-3/+22
| | | | | | revert the accidentally committed changes to LLVMSymbolize.cpp llvm-svn: 217021
* Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-09-031-79/+128
| | | | | | | | | | | | | | | | for MADD, SUB, and OR."" This reapplies r216805 with a fix to a copy-past error, which resulted in an incorrect register class. Original commit message: Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 217019
* [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.Juergen Ributzka2014-09-031-187/+164
| | | | | | | | | | | There is already target-dependent instruction selection support for Adds/Subs to support compares and the intrinsics with overflow check. This takes advantage of the existing infrastructure to also support Add/Sub, which allows the folding of immediates, sign-/zero-extends, and shifts. This fixes rdar://problem/18207316. llvm-svn: 217007
* Only emit movw on ARMv6T2+Renato Golin2014-09-021-1/+2
| | | | | | | | Fix PR18364. Patch by Dimitry Andric. llvm-svn: 216989
* [FastISel][AArch64] Use the target-dependent selection code for shifts first.Juergen Ributzka2014-09-021-6/+6
| | | | | | | | | | | | This uses the target-dependent selection code for shifts first, which allows us to create better code for shifts with immediates and sign-/zero-extend folding. Vector type are not handled yet and the code falls back to target-independent instruction selection for these cases. This fixes rdar://problem/17907920. llvm-svn: 216985
* [FastISel][AArch64] Use a new helper function to determine if a value type ↵Juergen Ributzka2014-09-021-6/+25
| | | | | | | | | | | | is supported. NFCI. FastISel for AArch64 supports more value types than are actually legal. Use a dedicated helper function to reflect this. It is very similar to the isLoadStoreTypeLegal function, with the exception that vector types are not supported yet. llvm-svn: 216984
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-0265-7217/+45
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* [X86] Allow atomic operations using immediates to avoid using a registerRobin Morisset2014-09-023-38/+167
| | | | | | | | | | | | | | | | The only valid lowering of atomic stores in the X86 backend was mov from register to memory. As a result, storing an immediate required a useless copy of the immediate in a register. Now these can be compiled as a simple mov. Similarily, adding/and-ing/or-ing/xor-ing an immediate to an atomic location (but through an atomic_store/atomic_load, not a fetch_whatever intrinsic) can now make use of an 'add $imm, x(%rip)' instead of using a register. And the same applies to inc/dec. This second point matches the first issue identified in http://llvm.org/bugs/show_bug.cgi?id=17281 llvm-svn: 216980
* [FastISel][AArch64] Move over to target-dependent instruction selection only.Juergen Ributzka2014-09-021-41/+133
| | | | | | | | | | | This change moves FastISel for AArch64 to target-dependent instruction selection only. This change replicates the existing target-independent behavior, therefore there are no changes to the unit tests or new tests. Future changes will take advantage of this change and update functionality and unit tests. llvm-svn: 216955
* Refactor LowerFABS and LowerFNEG into one function (x86) (NFC)Sanjay Patel2014-09-021-42/+31
| | | | | | | | | We duplicate ~30 lines of code to lower FABS and FNEG for x86, so this patch combines them into one function. No functional change intended, so no additional test cases. Test-suite behavior is unchanged. Differential Revision: http://reviews.llvm.org/D5064 llvm-svn: 216942
* CodeGen: Handle va_start in the entry blockReid Kleckner2014-09-021-2/+2
| | | | | | | | | Also fix a small copy-paste bug in X86ISelLowering where Chain should have been used in place of DAG.getEntryToken(). Fixes PR20828. llvm-svn: 216929
* Fix left shifts of negative values in MipsDisassembler.Alexey Samsonov2014-09-021-15/+15
| | | | | | This bug was reported by UBSan. llvm-svn: 216920
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-025-6/+6
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* Fix signed integer overflow in PPCInstPrinter.Alexey Samsonov2014-09-021-1/+1
| | | | | | This bug was reported by UBSan. llvm-svn: 216917
* Add missing override on ARMAsmBackend's dtor.JF Bastien2014-09-021-2/+1
| | | | | | | | | | Test Plan: ninja check && ninja clang-test Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D5075 llvm-svn: 216912
* Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov2014-09-022-5/+5
| | | | | | | | | | | | | | | | | | | Summary: Left shift of negative integer is an undefined behavior, and is reported by UBSan. It's ok for imm values to be negative, so we can just replace left shifts with multiplications. Test Plan: check-llvm test suite Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5132 llvm-svn: 216910
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly ↵Aaron Ballman2014-09-021-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?)). NFC. llvm-svn: 216902
* Merge Extend and Shift into a UBFXDavid Xu2014-09-021-13/+15
| | | | llvm-svn: 216899
* [PowerPC] Guard against illegal selection of add for TargetConstant operandsHal Finkel2014-09-021-0/+7
| | | | | | | | | | | r208640 was reverted because it caused a self-hosting failure on ppc64. The underlying cause was the formation of ISD::ADD nodes with ISD::TargetConstant operands. Because we have no patterns for 'add' taking 'timm' nodes, these are selected as r+r add instructions (which is a miscompile). Guard against this kind of behavior in the future by making the backend crash should this occur (instead of silently generating invalid output). llvm-svn: 216897
* CodeGen: indicate Windows unwind data formatSaleem Abdulrasool2014-09-011-0/+2
| | | | | | | | The structures for Windows unwinding are shared across multiple platforms. Indicate the encoding to be used for the particular target. Use this to switch the unwind emitter instantiated by the AsmPrinter. llvm-svn: 216895
* Use an integer constant for FABS / FNEG (x86).Sanjay Patel2014-09-011-14/+6
| | | | | | | | | | | | | | | | This change will ease refactoring LowerFABS() and LowerFNEG() since they have a lot of overlap. Remove the creation of a floating point constant from an integer because it's going to be used for a bitwise integer op anyway. No change to codegen expected, but the verbose comment string for asm output may change from float values to hex (integer), depending on whether the constant already exists or not. Differential Revision: http://reviews.llvm.org/D5052 llvm-svn: 216889
* [asan-assembly-instrumentation] Prologue and epilogue are moved out from ↵Yuri Gorshenin2014-09-014-173/+306
| | | | | | | | | | | | InstrumentMemOperand(). Reviewers: eugenis Subscribers: llvm-commits Differential revision: http://reviews.llvm.org/D4923 llvm-svn: 216879
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-014-62/+88
| | | | | | | | | | | | This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. llvm-svn: 216874
* Revert "[asan-assembly-instrumentation] Prologue and epilogue are moved out ↵Yuri Gorshenin2014-09-013-305/+172
| | | | | | | | from InstrumentMemOperand()." This reverts commit 895aa397038b8de86d83ac0997a70949a486e112. llvm-svn: 216872
* [asan-assembly-instrumentation] Prologue and epilogue are moved out from ↵Yuri Gorshenin2014-09-013-172/+305
| | | | | | InstrumentMemOperand(). llvm-svn: 216869
* Remove 'virtual' keyword from methods markedwith 'override' keyword.Craig Topper2014-08-3013-64/+61
| | | | llvm-svn: 216823
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-308-14/+14
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* JIT support has been added awhile ago.Brad Smith2014-08-301-2/+0
| | | | llvm-svn: 216819
* Revert r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-08-301-119/+73
| | | | | | | | for MADD, SUB, and OR." I think this broke the build bot. Reverting it for now until I have time to take a closer look. llvm-svn: 216813
* [MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.Juergen Ributzka2014-08-291-73/+119
| | | | | | | | | | Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 216805
* [FastISel][AArch64] Use the correct register class for branches.Juergen Ributzka2014-08-291-7/+9
| | | | | | | | Also constrain the register class for branches. This fixes rdar://problem/18181496. llvm-svn: 216804
* Make isValidMCLOHType take unsigned instead of enum to avoid loading invalid ↵Alexey Samsonov2014-08-291-3/+2
| | | | | | enum values llvm-svn: 216797
* AArch64: Silence -Wabsolute-value warning with std::absReid Kleckner2014-08-291-1/+2
| | | | llvm-svn: 216794
* Speculative build fix for const, gcc, and ArrayRef overloadsReid Kleckner2014-08-291-3/+3
| | | | llvm-svn: 216793
* Fix typos in comments, NFCRobin Morisset2014-08-295-8/+6
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* Add a const and munge some commentsReid Kleckner2014-08-291-3/+5
| | | | llvm-svn: 216781
* musttail: Forward regparms of variadic functions on x86_64Reid Kleckner2014-08-292-71/+154
| | | | | | | | | | | | | | | | | | | | | | Summary: If a variadic function body contains a musttail call, then we copy all of the remaining register parameters into virtual registers in the function prologue. We track the virtual registers through the function body, and add them as additional registers to pass to the call. Because this is all done in virtual registers, the register allocator usually gives us good code. If the function does a call, however, it will have to spill and reload all argument registers (ew). Forwarding regparms on x86_32 is not implemented because most compilers don't support varargs in 32-bit with regparms. Reviewers: majnemer Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5060 llvm-svn: 216780
* Verifier: Don't reject varargs callee cleanup functionsReid Kleckner2014-08-291-7/+2
| | | | | | | | | | | | | | | | | | We've rejected these kinds of functions since r28405 in 2006 because it's impossible to lower the return of a callee cleanup varargs function. However there are lots of legal ways to leave such a function without returning, such as aborting. Today we can leave a function with a musttail call to another function with the correct prototype, and everything works out. I'm removing the verifier check declaring that a normal return from such a function is UB. Reviewed By: nlewycky Differential Revision: http://reviews.llvm.org/D5059 llvm-svn: 216779
* Remove spurious mask operations from AArch64 add->compares on 16 and 8 bit ↵Louis Gerbarg2014-08-291-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | values This patch checks for DAG patterns that are an add or a sub followed by a compare on 16 and 8 bit inputs. Since AArch64 does not support those types natively they are legalized into 32 bit values, which means that mask operations are inserted into the DAG to emulate overflow behaviour. In many cases those masks do not change the result of the processing and just introduce a dependent operation, often in the middle of a hot loop. This patch detects the relevent DAG patterns and then tests to see if the transforms are equivalent with and without the mask, removing the mask if possible. The exact mechanism of this patch was discusses in http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/074444.html There is a reasonably good chance there are missed oppurtunities due to similiar (but not identical) DAG patterns that could be funneled into this test, adding them should be simple if we see test cases. Tests included. rdar://13754426 llvm-svn: 216776
* X86: Fix conflict over ESI between base register and rep;movslReid Kleckner2014-08-292-6/+36
| | | | | | | | | | | | | | The new solution is to not use this lowering if there are any dynamic allocas in the current function. We know up front if there are dynamic allocas, but we don't know if we'll need to create stack temporaries with large alignment during lowering. Conservatively assume that we will need such temporaries. Reviewed By: hans Differential Revision: http://reviews.llvm.org/D5128 llvm-svn: 216775
* [X86] Refactor X86ISelDAGToDAG::SelectAtomicLoadArith - NFCRobin Morisset2014-08-291-10/+17
| | | | | | | | | | | | | | | | | | | Summary: Mostly renaming the (not very explicit) variables Tmp0, .. Tmp4, and grouping related statements together, along with a few lines of comments for the surprising parts. No functional change intended. Test Plan: make check-all Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5088 llvm-svn: 216768
* [FastISel][AArch64] Fix an incorrect kill flag due to a bug in SelectTrunc.Juergen Ributzka2014-08-291-6/+13
| | | | | | | | | | | | | | | | | | | | When we select a trunc instruction we don't emit any code if the type is already i32 or smaller. This is because the instruction that uses the truncated value will deal with it. This behavior can incorrectly transfer a kill flag, which was meant for the result of the truncate, onto the source register. %2 = trunc i32 %1 to i16 ... = ... %2 -> ... = ... vreg1 <kill> ... = ... %1 ... = ... vreg1 This commit fixes this by emitting a COPY instruction, so that the result and source register are distinct virtual registers. This fixes rdar://problem/18178188. llvm-svn: 216750
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-296-0/+54
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* AArch64: only try to get operand of a known node.Tim Northover2014-08-291-5/+5
| | | | | | | A bug in r216725 meant we tried to discover the type of a SETCC before confirming the node actually was a SETCC. llvm-svn: 216734
* typoSanjay Patel2014-08-291-1/+1
| | | | llvm-svn: 216732
* [NVPTX] Make the alignment an explicit argument to ldu/ldgJingyue Wu2014-08-291-20/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Instead of specifying the alignment as metadata which may be destroyed by transformation passes, make the alignment the second argument to ldu/ldg intrinsic calls. Test Plan: ldu-ldg.ll ldu-i8.ll ldu-reg-plus-offset.ll Reviewers: eliben, meheff, jholewinski Reviewed By: meheff, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D5093 llvm-svn: 216731
* AArch64: skip select/setcc combine in complex case.Tim Northover2014-08-291-8/+10
| | | | | | | | | | | In an llvm-stress generated test, we were trying to create a v0iN type and asserting when that failed. This case could probably be handled by the function, but not without added complexity and the situation it arises in is sufficiently odd that there's probably no benefit anyway. Should fix PR20775. llvm-svn: 216725
* [AArch64] FPLoadBalancing: move ownership of the chain to its current ↵Arnaud A. de Grandmaison2014-08-291-5/+14
| | | | | | | | | | | | | | | | | accumulator register and forget about the previously used accumulator. Coming up with a simple testcase is not easy, as this highly depends on what the register allocator is doing: this issue showed up while working with the PBQP allocator, which produced a different allocation scheme. A testcase would need to come up with chain starting in D[0-7], then moving to D[8-15], followed by a call to a function whose regmask clobbers the starting accumulator in D[0-7], then another use of the chain. Fixed some formatting, added some invariant checks while there. llvm-svn: 216721
* [SKX] Enable lowering of integer CMP operations.Robert Khasanov2014-08-291-9/+75
| | | | | | | | | | Added new types to Legalizer. Fixed getSetCCResultType function Added lowering tests. Reviewed by Elena Demikhovsky. llvm-svn: 216717
* [AArch64] Fix some failures exposed by value type v4f16 and v8f16.Jiangning Liu2014-08-292-2/+11
| | | | | | | 1) Add some missing bitcast patterns for v8f16. 2) Add type promotion for operand of ld/st operations. llvm-svn: 216706
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