summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Add Simple return instruction to Mips fast-iselReed Kotler2014-04-291-2/+58
| | | | | | | | | | Reviewers: dsanders Reviewed by: dsanders Differential Revision: http://reviews.llvm.org/D3430 llvm-svn: 207565
* [mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements ↵Daniel Sanders2014-04-291-2/+2
| | | | | | | | | | | | | | that were missed Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3548 llvm-svn: 207558
* [mips] Remove more redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders2014-04-291-10/+6
| | | | | | | | | | | | Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3547 llvm-svn: 207551
* [mips] Remove redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders2014-04-293-21/+12
| | | | | | | | | | | | Summary: The MipsPat class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3546 llvm-svn: 207548
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-291-0/+6
| | | | llvm-svn: 207526
* [mips][msa] Fix element extraction where the index is variable.Daniel Sanders2014-04-291-0/+52
| | | | | | | | | | | | | | Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
* Centralize the handling of the thumb bit.Rafael Espindola2014-04-292-7/+3
| | | | | | | | | | | | | This patch centralizes the handling of the thumb bit around MCStreamer::isThumbFunc and makes isThumbFunc handle aliases. This fixes a corner case, but the main advantage is having just one way to check if a MCSymbol is thumb or not. This should still be refactored to be ARM only, but at least now it is just one predicate that has to be refactored instead of 3 (isThumbFunc, ELF_Other_ThumbFunc, and SF_ThumbFunc). llvm-svn: 207522
* X86: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-31/+35
| | | | | | rdar://problem/16660411 llvm-svn: 207518
* ARM: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-31/+30
| | | | | | rdar://problem/16660411 llvm-svn: 207517
* AArch64: Mark vector long multiplication as expand.Benjamin Kramer2014-04-291-0/+5
| | | | | | | There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. llvm-svn: 207515
* AVX-512: optimized a shuffle pattern to VINSERTI64x4.Elena Demikhovsky2014-04-292-0/+44
| | | | | | Added intrinsics for VPERMT2PS/PD/D/Q instructions. llvm-svn: 207513
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2910-23/+21
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. llvm-svn: 207511
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2922-130/+137
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2927-132/+141
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2922-209/+208
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2911-86/+87
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. MSP430 edition llvm-svn: 207507
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2938-399/+397
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2919-109/+113
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. NVPTX edition llvm-svn: 207505
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2924-306/+311
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. PowerPC edition llvm-svn: 207504
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2939-305/+316
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2919-155/+157
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition llvm-svn: 207502
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2915-115/+116
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. XCore edition llvm-svn: 207501
* [ARM64]Fix a bug about incorrect operand order in an EXT instruction, which ↵Hao Liu2014-04-291-3/+9
| | | | | | is introduced by r207485. llvm-svn: 207500
* [ARM64]Fix a bug when lowering shuffle vector to an EXT instruction.Hao Liu2014-04-291-28/+23
| | | | | | E.g. Mask like <-1, -1, 1, ...> will generate incorrect EXT index. llvm-svn: 207485
* None of these targets actually define their own CFI_INSTRUCTIONEric Christopher2014-04-294-19/+27
| | | | | | | opcode so there's no reason to use the target namespace for it rather than TargetOpcode. llvm-svn: 207475
* 80-column fixups.Eric Christopher2014-04-291-3/+5
| | | | llvm-svn: 207474
* 80-column, tab characters, comment fixups.Eric Christopher2014-04-291-43/+44
| | | | llvm-svn: 207473
* Fix 80-columns, tab characters, and comments.Eric Christopher2014-04-291-18/+20
| | | | llvm-svn: 207472
* [X86] Add more details in the comments of ↵Quentin Colombet2014-04-281-2/+16
| | | | | | X86TargetLowering::getScalingFactorCost. llvm-svn: 207432
* [ARM64] Fix an issue where we were always assuming a copy was coming from a ↵Chad Rosier2014-04-281-3/+3
| | | | | | D subregister. llvm-svn: 207423
* ARM: stop passing unused values up the TableGen hierarchy.Tim Northover2014-04-282-12/+8
| | | | | | | | It's bad enough that I have to look up 5 different levels of TableGen class definitions to work out what bits go where in a simple NEON instruction anyway, without having to keep track of umpteen unused parameters. llvm-svn: 207420
* Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.Patrik Hagglund2014-04-284-17/+15
| | | | | | | | | | X86_MAX_OPERANDS is changed to unsigned. Also, add range-based for loops for affected loops. This in turn needed an ArrayRef instead of a pointer-to-array in InternalInstruction. llvm-svn: 207413
* ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.Tim Northover2014-04-282-1/+14
| | | | | | | | | | | Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
* [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.Hao Liu2014-04-281-2/+4
| | | | llvm-svn: 207399
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-285-6/+6
| | | | llvm-svn: 207397
* [C++] Use 'nullptr'.Craig Topper2014-04-2871-137/+142
| | | | llvm-svn: 207394
* Add emitThumbSet to the arm target streamer.Rafael Espindola2014-04-273-30/+28
| | | | | | | This fixes the asm printer implementation and lets the parser be unaware of what .thumb_set is. llvm-svn: 207381
* Convert SelectionDAG::MorphNodeTo to use ArrayRef.Craig Topper2014-04-272-3/+5
| | | | llvm-svn: 207378
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-276-40/+36
| | | | llvm-svn: 207377
* Convert one last signature of getNode to take an ArrayRef of SDUse.Craig Topper2014-04-271-1/+2
| | | | llvm-svn: 207376
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-2716-60/+60
| | | | llvm-svn: 207374
* X86TTI: Adjust sdiv cost now that we can lower it on plain SSE2.Benjamin Kramer2014-04-271-0/+5
| | | | | | | Includes a fix for a horrible typo that caused all SDIV costs to be slightly off :) llvm-svn: 207371
* X86: If SSE4.1 is missing lower SMUL_LOHI of v4i32 to pmuludq and fix up the ↵Benjamin Kramer2014-04-271-2/+17
| | | | | | | | high parts. This is more expensive than pmuldq but still cheaper than scalarizing the whole thing. llvm-svn: 207370
* Avoid using MCSymbolData on the asm streamer.Rafael Espindola2014-04-272-28/+13
| | | | | | | | Only the object streamers need to track if a symbol should be marked thumb or not. This ports the ELF case. The COFF case is not ported since it is currently not working for some other reason (I will report a bug). llvm-svn: 207366
* ARM: MSVC does not support = defaultSaleem Abdulrasool2014-04-271-1/+1
| | | | | | | Explicitly "implement" the destructor as MSVC does not support defaulted methods yet. llvm-svn: 207350
* Add WoA object file emission supportSaleem Abdulrasool2014-04-277-17/+163
| | | | | | | | | | | | | | | | | | | | | | Introduce support for WoA PE/COFF object file emission from LLVM. Add the new target specific PE/COFF Streamer (ARMWinCOFFStreamer) that handles the ARM specific behaviour of PE/COFF object emission. ARM exception information is not yet emitted and is a TODO item. The ARM specific object writer (ARMWinCOFFObjectWriter) handles the ARM specific relocation handling in conjunction with the WinCOFFObjectWriter in the MC layer. The MC layer needs to be updated to deal with the relocation adjustments. Branch relocations are adjusted by 4 bytes (unlikely their ELF counterparts). Minor tweaks to switch multiple conditional checks into equivalent switch statements. The ObjectFileInfo is updated to relax the object file setup for Windows COFF. Move the architecture checks into an assertion. Windows COFF is currently only supported on x86, x86_64, and ARM (thumb). Rather than defaulting to ELF, we will refuse to generate an object file. This is better though as you do not get an (arbitrary) object file which is different from the request. llvm-svn: 207345
* MC: create X86WinCOFFStreamer for target specific behaviourSaleem Abdulrasool2014-04-274-1/+62
| | | | | | | | | | This introduces a target specific streamer, X86WinCOFFStreamer, which handles the target specific behaviour (e.g. WinEH). This is mostly to ensure that differences between ARM and X86 remain disjoint and do not accidentally cross boundaries. This is the final staging change for enabling object emission for Windows on ARM. llvm-svn: 207344
* ARM: Support SingleParameterDotFile on WoASaleem Abdulrasool2014-04-271-0/+1
| | | | | | | | | Currently, the integrated assembler is the only choice for assembling Windows on ARM binaries. IAS supports the .file <filename> directive which emits the file symbol into the resulting object binary. Mark the GNU COFF information to indicate support for this feature. llvm-svn: 207341
* Replace std::vector with SmallVector for some small, known size vectors.Craig Topper2014-04-261-4/+4
| | | | llvm-svn: 207330
* Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer ↵Craig Topper2014-04-269-72/+53
| | | | | | and size. llvm-svn: 207329
OpenPOWER on IntegriCloud