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* Added TargetPassConfig::setOptAndrew Trick2012-02-081-0/+2
| | | | llvm-svn: 150093
* Move pass configuration out of pass constructors: TailDuplicate::PreRegAllocAndrew Trick2012-02-081-2/+2
| | | | llvm-svn: 150091
* Use TSFlag bit to describe instruction properties.Brendon Cahoon2012-02-086-314/+208
| | | | | | | | Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. llvm-svn: 150078
* Fixed a bug in printing "cmp" pseudo ops.Elena Demikhovsky2012-02-084-41/+115
| | | | | | | | | | | | | | | | | | | | | | > This IR code > %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14) > fails with assertion: > > llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed. > 0 llc 0x0000000001355803 > 1 llc 0x0000000001355dc9 > 2 libpthread.so.0 0x00007f79a30575d0 > 3 libc.so.6 0x00007f79a23a1945 gsignal + 53 > 4 libc.so.6 0x00007f79a23a2f21 abort + 385 > 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240 > 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119 I added the full testing for all possible pseudo-ops of cmp. I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp. You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in. llvm-svn: 150068
* Remove a couple unneeded intrinsic patternsCraig Topper2012-02-081-6/+0
| | | | llvm-svn: 150067
* Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. ↵Craig Topper2012-02-082-32/+15
| | | | | | Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. llvm-svn: 150060
* [fast-isel] Add support for SUBs with non-legal types.Chad Rosier2012-02-081-0/+5
| | | | llvm-svn: 150047
* [fast-isel] Add support for ORs with non-legal types.Chad Rosier2012-02-081-2/+13
| | | | llvm-svn: 150045
* [fast-isel] Add support for indirect branches.Chad Rosier2012-02-071-0/+13
| | | | llvm-svn: 150014
* Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.Evan Cheng2012-02-074-21/+52
| | | | llvm-svn: 150008
* Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexedEvan Cheng2012-02-071-24/+58
| | | | | | | | load / store) if the ADD / SUB has a live definition of CPSR. Bug reported by David Meyer. Alas, no test case. llvm-svn: 149970
* Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.Craig Topper2012-02-072-22/+32
| | | | llvm-svn: 149968
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-0742-151/+106
| | | | llvm-svn: 149961
* [fast-isel] Add support for ADDs with non-legal types.Chad Rosier2012-02-061-5/+34
| | | | llvm-svn: 149934
* Add TargetPassConfig to the PassManager for use inside passesAndrew Trick2012-02-061-3/+5
| | | | llvm-svn: 149926
* Enable streaming of bitcodeDerek Schuff2012-02-065-8/+8
| | | | | | | This CL delays reading of function bodies from initial parse until materialization, allowing overlap of compilation with bitcode download. llvm-svn: 149918
* Remove some dead code and tidy things up now that vectors use ConstantDataVectorChris Lattner2012-02-062-25/+4
| | | | | | instead of always using ConstantVector. llvm-svn: 149912
* [unwind removal] We no longer have 'unwind' instructions being generated, soBill Wendling2012-02-062-8/+0
| | | | | | remove the code that handles them. llvm-svn: 149901
* X86: Don't call malloc for 4 bits. No functionality change.Benjamin Kramer2012-02-061-4/+3
| | | | llvm-svn: 149866
* Hexagon: Remove forbidden iostream includes (it introduces static initializers)Benjamin Kramer2012-02-068-73/+46
| | | | | | Reorder includes while at it. llvm-svn: 149863
* Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd ↵Craig Topper2012-02-064-84/+70
| | | | | | decoding. llvm-svn: 149859
* DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng2012-02-051-1/+1
| | | | llvm-svn: 149846
* Remove dead test: this was already checked and handled a few linesDuncan Sands2012-02-051-5/+0
| | | | | | above. llvm-svn: 149841
* Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands2012-02-053-2/+3
| | | | llvm-svn: 149834
* Don't initialize CV in terms of itself! Spotted by GCC.Duncan Sands2012-02-051-4/+4
| | | | llvm-svn: 149833
* Begin fleshing out more convenience predicates in llvm::Triple andChandler Carruth2012-02-051-17/+7
| | | | | | | | | | convert at least one client over to use them. Subsequent patches both to LLVM and Clang will try to convert more people over to a common set of predicates. This round of predicates is focused on OS-categorization predicates. llvm-svn: 149815
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-058-0/+8
| | | | llvm-svn: 149814
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-058-22/+20
| | | | llvm-svn: 149809
* Convert some assert(0) in default of switch statements to llvm_unreachable.Craig Topper2012-02-051-10/+7
| | | | llvm-svn: 149808
* Add target specific node for PMULUDQ. Change patterns to use it and custom ↵Craig Topper2012-02-054-69/+69
| | | | | | lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. llvm-svn: 149807
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-052-96/+25
| | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. llvm-svn: 149800
* Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased ↵Craig Topper2012-02-051-125/+0
| | | | | | to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. llvm-svn: 149795
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-0422-87/+62
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149716
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | llvm-svn: 149714
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149706
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149704
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. llvm-svn: 149683
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. llvm-svn: 149680
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0322-154/+401
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-034-15/+15
| | | | llvm-svn: 149671
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-034-3/+16
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | llvm-svn: 149655
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-2/+2
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. llvm-svn: 149640
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | llvm-svn: 149601
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-024-0/+67
| | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. llvm-svn: 149600
* Unbreak the MSVC build.Francois Pichet2012-02-021-1/+1
| | | | llvm-svn: 149599
* Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames2012-02-021-2/+29
| | | | llvm-svn: 149597
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