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* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-173-19/+17
| | | | | | Move ARM callee-saved lists into ARMCallingConv.td. llvm-svn: 148357
* Move X86 callee saved register lists to the X86CallConv .td file.Jakob Stoklund Olesen2012-01-173-37/+37
| | | | | | Add a trivial implementation of the getCallPreservedMask() hook. llvm-svn: 148347
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-3/+3
| | | | llvm-svn: 148338
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+4
| | | | llvm-svn: 148334
* Untabify.Devang Patel2012-01-171-12/+12
| | | | llvm-svn: 148322
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-2/+1
| | | | | | displacement. llvm-svn: 148321
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-51/+113
| | | | llvm-svn: 148312
* Fix warning.Nadav Rotem2012-01-171-1/+1
| | | | llvm-svn: 148301
* Fix 11769.Nadav Rotem2012-01-171-0/+7
| | | | | | | | In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. llvm-svn: 148298
* Remove unnecessary AVX check from an assert. hasSSE2 is enough.Craig Topper2012-01-171-2/+1
| | | | llvm-svn: 148295
* Moving options declarations around.Andrew Trick2012-01-171-8/+0
| | | | | | More short term hackery until we have a way to configure passes that work on LiveIntervals. llvm-svn: 148289
* Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. ↵Craig Topper2012-01-171-0/+5
| | | | | | Probably could use better handling in DAG combine or getNode. Fixes PR11772. llvm-svn: 148285
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-163-10/+1
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
| | | | | | No test case: output assembly will be identical. llvm-svn: 148261
* Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman2012-01-161-1/+1
| | | | llvm-svn: 148240
* Get rid of unused codegen-only instruction.Eli Friedman2012-01-162-12/+0
| | | | llvm-svn: 148239
* Give priority to AVX over SSE for 128-bit floating point unpck instructions.Craig Topper2012-01-161-34/+34
| | | | llvm-svn: 148233
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+2
| | | | | | unused variables). llvm-svn: 148230
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-1/+22
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-153-87/+50
| | | | | | CodeGen. llvm-svn: 148218
* Fix the memop type on a couple 256-bit AVX instructions that were using ↵Craig Topper2012-01-141-4/+4
| | | | | | f128mem instead of f256mem. llvm-svn: 148196
* Add a bunch of AVX instructions to the folding tables. Also fixed the ↵Craig Topper2012-01-141-69/+139
| | | | | | alignment on 256-bit AVX2 instructions. llvm-svn: 148194
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-0/+5
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Fix pasto from r146196.Chad Rosier2012-01-141-2/+2
| | | | llvm-svn: 148167
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-134-45/+51
| | | | | | | | | | The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
* Revert r148131, it was committed before it was ready.Devang Patel2012-01-131-46/+40
| | | | llvm-svn: 148134
* Refactor.Devang Patel2012-01-131-40/+46
| | | | llvm-svn: 148131
* Convert SHUFPD with the same register for both sources to PSHUFD if it would ↵Craig Topper2012-01-132-1/+20
| | | | | | prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. llvm-svn: 148112
* use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 ↵Craig Topper2012-01-131-3/+6
| | | | | | vs SSE1. llvm-svn: 148109
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ↵Craig Topper2012-01-134-37/+62
| | | | | | ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. llvm-svn: 148108
* Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper2012-01-131-0/+8
| | | | | | v4i64 and v8i32. llvm-svn: 148106
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-131-1/+10
| | | | llvm-svn: 148105
* Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes ↵Craig Topper2012-01-131-0/+2
| | | | | | PR11750. llvm-svn: 148101
* Fix typo in PerformAddCombine that caused any vector type to be checked for ↵Craig Topper2012-01-131-1/+1
| | | | | | horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. llvm-svn: 148096
* Fix off-by-one error.Bill Wendling2012-01-131-1/+1
| | | | llvm-svn: 148077
* Fix the code that was WRONG.Bill Wendling2012-01-121-13/+6
| | | | | | | The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. llvm-svn: 148064
* Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky2012-01-121-1/+5
| | | | | | | lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. llvm-svn: 148044
* Support segmented stacks on 64-bit FreeBSD.Rafael Espindola2012-01-121-2/+8
| | | | | | | This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. llvm-svn: 148041
* Support segmented stacks on win32.Rafael Espindola2012-01-121-7/+17
| | | | | | | Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. llvm-svn: 148040
* Rename X86ATTAsmParser -> X86AsmParserDevang Patel2012-01-122-19/+18
| | | | | | We are using one parser to parse att as well as intel style syntax. llvm-svn: 148032
* After Jakob's r147938 exception handling on i386 was completely broken.Benjamin Kramer2012-01-121-0/+7
| | | | | | | | | Restore the (obviously wrong) behavior from before r147938 without relying on undefined behavior. Add a fat FIXME note. This should fix nightly tester failures. llvm-svn: 148030
* Fix a bug in the AVX 256-bit shuffle code in cases where the splat element ↵Nadav Rotem2012-01-121-1/+1
| | | | | | | | is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. llvm-svn: 148027
* X86: Generalize the x << (y & const) optimization to also catch masks with ↵Benjamin Kramer2012-01-121-21/+25
| | | | | | more set bits set than 31 or 63. llvm-svn: 148024
* Add predicate method check match memory operand size, if available.Devang Patel2012-01-122-17/+96
| | | | | | In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
* Add intel style operand parser skeleton. Devang Patel2012-01-121-1/+97
| | | | | | This is a work in progress. llvm-svn: 148002
* Switch all of the uses of my InsertDAGNode helper to follow the exactChandler Carruth2012-01-121-8/+22
| | | | | | | | | | | | | | | | | | | | same pattern. We already had this pattern is a few places, but others tried to make a rough approximation of an actual DAG structure. As not everywhere went to this trouble, nothing could rely on this being done. In fact, I've checked all references to these node Ids, and the ones that are using the topo-sort properties are actually satisfied with a strict-weak-ordering. The requirement appears to be that Use >= Def. I've added a big blurb of comments to this bit of the transform to clarify why the order is so important for the next reader of the code. I'm starting with this change as it is very small, and trivially reverted if something breaks or the >= above really does need to be >. If that proves the case, we can hide the problem by reverting this patch, but the problem exists elsewhere as well, and so a more comprehensive solution will be needed. llvm-svn: 148001
* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* Support segmented stacks on mac.Rafael Espindola2012-01-112-18/+68
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Generate the segmented stack prologue for fastcc too.Rafael Espindola2012-01-111-1/+2
| | | | | | Patch by Brian Anderson. llvm-svn: 147958
* Revert r147945 which disabled an addressing mode transformation. I hadChandler Carruth2012-01-111-4/+0
| | | | | | | | | hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
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