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* Custom lower vector shift intrinsics to target specific nodes and remove the ↵Craig Topper2012-01-232-385/+156
| | | | | | patterns that are no longer needed. llvm-svn: 148684
* Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 ↵Craig Topper2012-01-232-30/+2
| | | | | | loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. llvm-svn: 148672
* Combine X86 CMPPD and CMPPS node types. Simplifies selection code and ↵Craig Topper2012-01-224-25/+26
| | | | | | pattern matching. llvm-svn: 148670
* Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ ↵Craig Topper2012-01-224-87/+66
| | | | | | X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. llvm-svn: 148667
* Use Attributes::None instead of 0 after r148553 change on Attributes from ↵Nicolas Geoffray2012-01-221-1/+1
| | | | | | unsigned to their own class. llvm-svn: 148665
* Add target specific ISD node types for SSE/AVX vector shuffle instructions ↵Craig Topper2012-01-224-273/+410
| | | | | | and change all the code that used to create intrinsic nodes to create the new nodes instead. llvm-svn: 148664
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-228-27/+186
| | | | | | Patch by Ana Pazos! llvm-svn: 148658
* Make code a little less verbose.Craig Topper2012-01-221-7/+5
| | | | llvm-svn: 148651
* Remove unused X86 ISD node type defines.Craig Topper2012-01-222-8/+0
| | | | llvm-svn: 148644
* Move some vector shift patterns into their instruction definitions.Craig Topper2012-01-221-48/+42
| | | | llvm-svn: 148643
* Add memory patterns for some of the fp<->integer conversion instructions. ↵Craig Topper2012-01-211-24/+28
| | | | | | Fold some patterns into instruction definitions. llvm-svn: 148641
* Remove unused variables.Benjamin Kramer2012-01-211-2/+0
| | | | llvm-svn: 148635
* Fix PR11819 introduced by r148537. I'd commit the test case, but the ↵Craig Topper2012-01-211-2/+2
| | | | | | generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. llvm-svn: 148632
* Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.Jim Grosbach2012-01-212-1/+6
| | | | llvm-svn: 148601
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-28/+16
| | | | llvm-svn: 148591
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-2056-299/+139
| | | | llvm-svn: 148578
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-0/+5
| | | | llvm-svn: 148570
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+3
| | | | llvm-svn: 148569
* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+3
| | | | | | | | We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. llvm-svn: 148568
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-6/+15
| | | | | | rdar://10724489 llvm-svn: 148560
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-202-36/+41
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* Remove a bunch of unused variable assignments.Benjamin Kramer2012-01-201-2/+1
| | | | | | Found by the clang static analyzer. llvm-svn: 148541
* Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. ↵Craig Topper2012-01-201-86/+86
| | | | | | As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. llvm-svn: 148537
* Add support for selecting 256-bit PALIGNR.Craig Topper2012-01-202-24/+81
| | | | llvm-svn: 148532
* Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman2012-01-202-3/+9
| | | | llvm-svn: 148513
* Silence warnings about mixing enums.Benjamin Kramer2012-01-191-3/+2
| | | | llvm-svn: 148495
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+78
| | | | llvm-svn: 148489
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-1/+1
| | | | | | displacement. llvm-svn: 148486
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+114
| | | | | | if available. llvm-svn: 148485
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
| | | | llvm-svn: 148473
* Folding table additions and fixes for AVX.Craig Topper2012-01-191-9/+21
| | | | llvm-svn: 148467
* Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.Craig Topper2012-01-193-129/+80
| | | | llvm-svn: 148466
* ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach2012-01-191-3/+4
| | | | llvm-svn: 148459
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
| | | | llvm-svn: 148456
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
| | | | llvm-svn: 148455
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-191-1/+2
| | | | | | | | | | | to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). llvm-svn: 148444
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-1/+4
| | | | llvm-svn: 148442
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-191-1/+1
| | | | llvm-svn: 148440
* Add experimental -x86-use-regmask command line option.Jakob Stoklund Olesen2012-01-181-0/+12
| | | | | | | | It adds register mask operands to x86 call instructions. Once all the backend passes support register mask operands, this will be permanently enabled. llvm-svn: 148438
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-186-1/+17
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-183-0/+69
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-16/+87
| | | | | | more desirable. llvm-svn: 148431
* Replace FIXME with explanatory comment.Jim Grosbach2012-01-181-1/+2
| | | | llvm-svn: 148427
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 llvm-svn: 148424
* Rename pattern for clarity.Jim Grosbach2012-01-181-4/+3
| | | | llvm-svn: 148422
* Tidy up. 80 columns.Jim Grosbach2012-01-181-13/+13
| | | | llvm-svn: 148401
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-185-38/+38
| | | | llvm-svn: 148400
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
| | | | | | | | | | Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. llvm-svn: 148366
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-181-0/+15
| | | | llvm-svn: 148364
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-185-2/+6
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
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