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* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-0612-204/+244
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Fix up -fstack-protector on linux to use the segmentEric Christopher2010-07-062-0/+27
| | | | | | | | | registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. llvm-svn: 107640
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-053-64/+38
| | | | llvm-svn: 107625
* Remove some unused/redundant code.Kalle Raiskila2010-07-052-20/+0
| | | | llvm-svn: 107622
* more tidying.Chris Lattner2010-07-051-2/+1
| | | | llvm-svn: 107615
* some notes about suboptimal insertps'sChris Lattner2010-07-051-0/+31
| | | | llvm-svn: 107613
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-053-19/+1
| | | | llvm-svn: 107610
* rip out the various v2f32 "mmx" handling logic, now that Chris Lattner2010-07-051-6/+6
| | | | | | v2f32 is illegal on x86. llvm-svn: 107609
* Just rip v2f32 support completely out of the X86 backend. InChris Lattner2010-07-041-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the example in the testcase, we now generate: _test1: ## @test1 movss 4(%esp), %xmm0 addss 8(%esp), %xmm0 movl 12(%esp), %eax movss %xmm0, (%eax) ret instead of: _test1: ## @test1 subl $20, %esp movl 24(%esp), %eax movq %mm0, (%esp) movq %mm0, 8(%esp) movss (%esp), %xmm0 addss 12(%esp), %xmm0 movss %xmm0, (%eax) addl $20, %esp ret v2f32 support did not work reliably because most of the X86 backend didn't know it was legal. It was apparently only added to support returning source-level v2f32 values in MMX registers in x86-32 mode. If ABI compatibility is important on this GCC-extended-vector type for some reason, then the frontend should generate IR that returns v2i32 instead of v2f32. However, we generally don't try very hard to be abi compatible on gcc extended vectors. llvm-svn: 107601
* fix PR7518 - terrible codegen of <2 x float>, by only markingChris Lattner2010-07-041-6/+16
| | | | | | | | v2f32 as legal in 32-bit mode. It is just as terrible there, but I just care about x86-64 and noone claims it is valuable in 64-bit mode. llvm-svn: 107600
* indentationChris Lattner2010-07-041-2/+3
| | | | llvm-svn: 107599
* Revert r107583. I no longer think that this is the way to solve the problem.Bill Wendling2010-07-041-2/+2
| | | | llvm-svn: 107585
* Mark sse_load_f32 and sse_load_f64 as having memory operandsBill Wendling2010-07-041-2/+2
| | | | | | | (SDNPMemOperand). This way when they're morphed the memory operands will be copied as well. llvm-svn: 107583
* Minor amendment to switch-lowering improvement.Eli Friedman2010-07-031-2/+10
| | | | llvm-svn: 107569
* Note switch-lowering inefficiency.Eli Friedman2010-07-031-0/+36
| | | | llvm-svn: 107565
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-031-0/+19
| | | | llvm-svn: 107560
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-031-0/+26
| | | | llvm-svn: 107558
* Add AVX SSE4.1 Horizontal Minimum and Position instructionBruno Cardoso Lopes2010-07-031-0/+3
| | | | llvm-svn: 107552
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-0316-66/+53
| | | | | | slots so it's always false. llvm-svn: 107550
* Add AVX SSE4.1 round instructionsBruno Cardoso Lopes2010-07-031-0/+76
| | | | llvm-svn: 107549
* Simple refactoring of SSE4.1 instructions, making room for the AVX formsBruno Cardoso Lopes2010-07-021-151/+117
| | | | llvm-svn: 107540
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-022-19/+89
| | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode llvm-svn: 107523
* Remove early IT block formation. It's not used.Evan Cheng2010-07-023-213/+6
| | | | llvm-svn: 107513
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-021-4/+21
| | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
* beautify outputGabor Greif2010-07-021-0/+1
| | | | llvm-svn: 107500
* use ArgOperand APIGabor Greif2010-07-021-2/+2
| | | | llvm-svn: 107498
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-022-4/+4
| | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. llvm-svn: 107487
* use ArgOperand API (found by my previous commit)Gabor Greif2010-07-021-6/+6
| | | | llvm-svn: 107482
* Shrink down SSE3 code by more multiclass refactoringBruno Cardoso Lopes2010-07-011-149/+99
| | | | llvm-svn: 107448
* Shrink down SSE3 code by some multiclass refactoring - 1st partBruno Cardoso Lopes2010-07-011-74/+17
| | | | llvm-svn: 107438
* ARM function alignments were off by a power of two. svn 83242 changedBob Wilson2010-07-011-1/+1
| | | | | | | | | getFunctionAlignment and the corresponding use of that value in the ARM asm printer, but now we're using the standard asm printer. The result of this was that function alignments were dropped completely for Thumb functions. Radar 8143571. llvm-svn: 107435
* Implement the "linker_private_weak" linkage type. This will be used forBill Wendling2010-07-013-2/+3
| | | | | | | | | | | | | | | | | | | | | | | Objective-C metadata types which should be marked as "weak", but which the linker will remove upon final linkage. However, this linkage isn't specific to Objective-C. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". Currently only supported on Darwin platforms. llvm-svn: 107433
* Move SSE3 Move patterns to a more appropriate sectionBruno Cardoso Lopes2010-07-011-30/+55
| | | | | | Add AVX SSE3 packed horizontal and & sub instructions llvm-svn: 107405
* Add AVX SSE3 packed addsub instructionsBruno Cardoso Lopes2010-07-011-23/+34
| | | | llvm-svn: 107404
* Enable on-demand fast-isel.Dan Gohman2010-07-011-1/+1
| | | | llvm-svn: 107377
* Fix X86FastISel's add folding to actually work, and not fall backDan Gohman2010-07-011-4/+8
| | | | | | to SelectionDAG. llvm-svn: 107376
* Add AVX SSE3 replicate and convert instructionsBruno Cardoso Lopes2010-07-011-22/+45
| | | | llvm-svn: 107375
* Teach X86FastISel to fold constant offsets and scaled indices inDan Gohman2010-07-011-14/+23
| | | | | | the same address. llvm-svn: 107373
* - Add AVX SSE2 Move doubleword and quadword instructions.Bruno Cardoso Lopes2010-07-014-17/+139
| | | | | | | | - Add encode bits for VEX_W - All 128-bit SSE 1 & SSE2 instructions that are described in the .td file now have a AVX encoded form already working. llvm-svn: 107365
* Move MOVD/MODQ code around, creating sections for each of themBruno Cardoso Lopes2010-06-301-52/+62
| | | | llvm-svn: 107308
* Add AVX SSE2 mask creation and conditional store instructionsBruno Cardoso Lopes2010-06-301-10/+36
| | | | llvm-svn: 107306
* Fix a bug introduced in r107211 where instructions with memory operands are ↵Bruno Cardoso Lopes2010-06-301-91/+78
| | | | | | declared as commutable llvm-svn: 107300
* Add AVX SSE2 packed integer extract/insert instructionsBruno Cardoso Lopes2010-06-301-17/+42
| | | | llvm-svn: 107293
* use ArgOperand APIGabor Greif2010-06-301-1/+1
| | | | llvm-svn: 107280
* Add AVX SSE2 integer unpack instructionsBruno Cardoso Lopes2010-06-301-10/+57
| | | | llvm-svn: 107246
* Add AVX SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-301-0/+14
| | | | llvm-svn: 107245
* Small refactoring of SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-301-45/+26
| | | | llvm-svn: 107243
* Add AVX SSE2 pack with saturation integer instructionsBruno Cardoso Lopes2010-06-301-0/+9
| | | | llvm-svn: 107241
* Add AVX SSE2 integer packed compare instructionsBruno Cardoso Lopes2010-06-301-0/+17
| | | | llvm-svn: 107240
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