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* Silence a clang warning about the deprecated (but perfectly reasonable inJohn McCall2009-12-161-2/+2
| | | | | | context) increment-of-bool idiom. llvm-svn: 91564
* Mark STREX* as earlyclobber for the success result register.Jim Grosbach2009-12-162-2/+2
| | | | llvm-svn: 91555
* Add encoding bits for some Thumb instructions. Plus explicitly set the top twoJohnny Chen2009-12-163-10/+18
| | | | | | bytes of Inst to 0x0000 for the benefit of the Thumb decoder. llvm-svn: 91496
* Re-enable 91381 with fixes.Evan Cheng2009-12-163-12/+40
| | | | llvm-svn: 91489
* Every anonymous namespace is different. Caught by clang++.John McCall2009-12-161-4/+0
| | | | llvm-svn: 91481
* Change indirect-globals to use a dedicated allocIndirectGV. This lets usJeffrey Yasskin2009-12-154-21/+15
| | | | | | | | | remove start/finishGVStub and the BufferState helper class from the MachineCodeEmitter interface. It has the side-effect of not setting the indirect global writable and then executable on ARM, but that shouldn't be necessary. llvm-svn: 91464
* Added encoding bits for the Thumb ISA. Initial checkin.Johnny Chen2009-12-153-348/+1219
| | | | llvm-svn: 91434
* Fix an encoding bug.Evan Cheng2009-12-151-1/+1
| | | | llvm-svn: 91417
* For fastcc on x86, let ECX be used as a return register after EAX and EDXKenneth Uildriks2009-12-151-1/+8
| | | | llvm-svn: 91410
* Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.Evan Cheng2009-12-151-1/+3
| | | | llvm-svn: 91405
* Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵Evan Cheng2009-12-154-3/+96
| | | | | | all zero's. llvm-svn: 91381
* nand atomic requires opposite operand orderingJim Grosbach2009-12-151-3/+9
| | | | llvm-svn: 91371
* Fix integer cast code to handle vector types.Dan Gohman2009-12-141-2/+11
| | | | llvm-svn: 91362
* Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguateJohnny Chen2009-12-141-0/+1
| | | | | | between BR_JTr and STREXD. llvm-svn: 91339
* v6 sync insn copy/paste errorJim Grosbach2009-12-141-1/+1
| | | | llvm-svn: 91333
* Add ARMv6 memory and sync barrier instructionsJim Grosbach2009-12-143-14/+45
| | | | llvm-svn: 91329
* Fixed encoding bits typo of ldrexd/strexd.Johnny Chen2009-12-141-2/+2
| | | | llvm-svn: 91327
* Thumb2 atomic operationsJim Grosbach2009-12-141-44/+83
| | | | llvm-svn: 91321
* fix an obvious bug found by clang++ and collapse a redundant if.Chris Lattner2009-12-141-7/+6
| | | | | | | | | | | Here's the diagnostic from clang: /Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context         printConstant(gv);                       ^ 1 diagnostic generated. llvm-svn: 91318
* correct selection requirements for thumb2 vs. arm versions of the barrier ↵Jim Grosbach2009-12-142-4/+6
| | | | | | intrinsics llvm-svn: 91313
* add Thumb2 atomic and memory barrier instruction definitionsJim Grosbach2009-12-141-0/+60
| | | | llvm-svn: 91310
* whitespaceJim Grosbach2009-12-141-1/+0
| | | | llvm-svn: 91307
* ARM memory barrier instructions are not predicableJim Grosbach2009-12-142-3/+20
| | | | llvm-svn: 91305
* add ldrexd/strexd instructionsJim Grosbach2009-12-141-2/+11
| | | | llvm-svn: 91284
* Whitespace changes, comment clarification. No functional changes.Bill Wendling2009-12-141-15/+26
| | | | llvm-svn: 91274
* atomic binary operations up to 32-bits wide.Jim Grosbach2009-12-141-5/+63
| | | | llvm-svn: 91260
* Do not allow uninitialize access during debug printingAnton Korobeynikov2009-12-131-2/+2
| | | | llvm-svn: 91232
* More info on this transformation.Eli Friedman2009-12-121-2/+15
| | | | llvm-svn: 91230
* Remove some stuff that's already implemented. Also, remove the note aboutEli Friedman2009-12-121-51/+0
| | | | | | merging x >u 5 and x <s 20 because it's impossible to implement. llvm-svn: 91228
* Disable r91104 for x86. It causes partial register stall which pessimize ↵Evan Cheng2009-12-121-12/+12
| | | | | | code in 32-bit. llvm-svn: 91223
* Implement variable-width shifts.Anton Korobeynikov2009-12-123-7/+170
| | | | | | No testcase yet - it seems we're exposing generic codegen bugs. llvm-svn: 91221
* Add comment about potential partial register stall.Evan Cheng2009-12-121-0/+5
| | | | llvm-svn: 91220
* Fix an obvious bug. No test case since LEA16r is not being used.Evan Cheng2009-12-121-1/+1
| | | | llvm-svn: 91219
* Framework for atomic binary operations. The emitter for the pseudo instructionsJim Grosbach2009-12-123-19/+150
| | | | | | | just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. llvm-svn: 91200
* Lower setcc branchless, if this is profitable.Anton Korobeynikov2009-12-112-2/+86
| | | | | | Based on the patch by Brian Lucas! llvm-svn: 91175
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-0/+1
| | | | llvm-svn: 91158
* memory barrier instructions by definition have side effects. This prevents ↵Jim Grosbach2009-12-111-1/+1
| | | | | | the post-RA scheduler from moving them around. llvm-svn: 91150
* Honour setHasCalls() set from isel.Anton Korobeynikov2009-12-111-0/+5
| | | | | | | This is used in some weird cases like general dynamic TLS model. This fixes PR5723 llvm-svn: 91144
* Store Register Exclusive should leave the source register Inst{3-0} unspecified.Johnny Chen2009-12-111-1/+1
| | | | llvm-svn: 91143
* Update properties.Jim Grosbach2009-12-111-2/+2
| | | | llvm-svn: 91140
* Add support to 3-addressify 16-bit instructions.Evan Cheng2009-12-112-88/+135
| | | | llvm-svn: 91104
* Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵Jim Grosbach2009-12-115-0/+152
| | | | | | progress. llvm-svn: 91090
* Add instruction encoding for DMB/DSBJim Grosbach2009-12-101-3/+11
| | | | llvm-svn: 91053
* Add memory barrier intrinsic support for ARM. Moving towards adding the ↵Jim Grosbach2009-12-103-1/+49
| | | | | | atomic operations intrinsics. llvm-svn: 91003
* Optimize splat of a scalar load into a shuffle of a vector load when it's ↵Evan Cheng2009-12-093-4/+93
| | | | | | | | | | | | legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-11/+1
| | | | | | isl lowering code. llvm-svn: 90925
* Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng2009-12-091-1/+1
| | | | | | primary used by selectdag passes. llvm-svn: 90922
* - Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng2009-12-082-0/+6
| | | | | | - Also support the 'q' NEON registers asm code. llvm-svn: 90894
* Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra ↵Anton Korobeynikov2009-12-081-1/+65
| | | | | | instruction. Patch inspired by Brian Lucas! llvm-svn: 90819
* Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman2009-12-071-1/+1
| | | | | | current form, it is too expensive in compile time. llvm-svn: 90781
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