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* Default TargetData alignment information for 128-bit floating-point types.Hal Finkel2012-02-261-0/+1
| | | | llvm-svn: 151473
* Revert r151278, breaks static linking.Hal Finkel2012-02-251-14/+6
| | | | | | | | | Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem. With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just has some pointers, not code). llvm-svn: 151433
* Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 ↵NAKAMURA Takumi2012-02-253-12/+20
| | | | | | | | | | | | lowering for i386-*-win32 targets. Patch by Joe Groff. [Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems: Clang raised a warning, and X86 LowerOperation would assert out for fptoui f64 to i32 because it improperly lowered to an illegal BUILD_PAIR. Here's a patch that addresses these issues. Let me know if any other changes are necessary. Thanks. llvm-svn: 151432
* Add definitions of floating point multiply add/sub and negative multiplyAkira Hatanaka2012-02-253-8/+71
| | | | | | add/sub instructions. llvm-svn: 151415
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-2416-98/+247
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* Remove unused cl::opt, make another opt static.Benjamin Kramer2012-02-242-4/+1
| | | | llvm-svn: 151398
* Thumb2 asm aliases for wide bitwise w/ immediate instructions.Jim Grosbach2012-02-241-0/+9
| | | | llvm-svn: 151384
* Add WIN_FTOL_* psudo-instructions to model the unique calling conventionMichael J. Spencer2012-02-245-32/+131
| | | | | | used by the Win32 _ftol2 runtime function. Patch by Joe Groff! llvm-svn: 151382
* X11/X2 loads around indirect calls on ppc64 should not be deleted.Hal Finkel2012-02-241-2/+4
| | | | llvm-svn: 151374
* Remove dead code.Richard Osborne2012-02-241-3/+1
| | | | | | Patch by Ahmed Charles llvm-svn: 151360
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-241-9/+0
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* comment fixJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151341
* some comment fixJia Liu2012-02-241-3/+3
| | | | llvm-svn: 151340
* comment fixJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151339
* replace a balnk with -Jia Liu2012-02-241-1/+1
| | | | llvm-svn: 151337
* 80 columns of Mips InstPrinter MakefileJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151332
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-245-35/+25
| | | | | | | | | | | | | I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
* Make sure the regs are low regs for tMUL size reduction.Jim Grosbach2012-02-241-1/+6
| | | | llvm-svn: 151318
* Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach2012-02-241-1/+13
| | | | | | | | | The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. llvm-svn: 151315
* When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman2012-02-241-0/+5
| | | | | | | bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. llvm-svn: 151310
* MCize function entry label emission on PowerPC64 properly.Roman Divacky2012-02-231-6/+14
| | | | llvm-svn: 151278
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-237-63/+240
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Fix the numbering of some of the registers and reclassify a couple of them.Brendon Cahoon2012-02-231-66/+64
| | | | | | Also, some basic clean up. Patch by Evandro Menezes. llvm-svn: 151266
* Remove unused variable.Duncan Sands2012-02-231-1/+0
| | | | llvm-svn: 151251
* Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng2012-02-231-0/+15
| | | | | | | | of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 llvm-svn: 151230
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-235-8/+312
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Allow the use of an alternate symbol for calculating a function's size.Hal Finkel2012-02-221-1/+5
| | | | | | | | | | | | | The standard function epilog includes a .size directive, but ppc64 uses an alternate local symbol to tag the actual start of each function. Until recently, binutils accepted the .size directive as: .size test1, .Ltmp0-test1 however, using this directive with recent binutils will result in the error: .size expression for XXX does not evaluate to a constant so we must use the label which actually tags the start of the function. llvm-svn: 151200
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-221-1/+1
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Remove extra semi-colons.Chad Rosier2012-02-223-4/+4
| | | | llvm-svn: 151169
* Efficient pattern for store truncate. Patch by Evandro Menezes.Sirish Pande2012-02-224-22/+7
| | | | llvm-svn: 151166
* Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper2012-02-221-2/+2
| | | | | | that weren't already const. llvm-svn: 151138
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-2212-46/+39
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Adding support for Microsoft's thiscall calling convention. LLVM side of ↵Aaron Ballman2012-02-221-2/+2
| | | | | | the patch. llvm-svn: 151123
* Clarify ARM calling conventions.Jakob Stoklund Olesen2012-02-221-0/+2
| | | | llvm-svn: 151113
* Use a function in MathExtras to do sign extension.Akira Hatanaka2012-02-221-1/+1
| | | | llvm-svn: 151107
* Calls don't really change the stack pointer.Jakob Stoklund Olesen2012-02-211-1/+2
| | | | | | | Even if a call instruction has %SP<imp-def> operands, it doesn't change the value of the stack pointer. llvm-svn: 151104
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-214-8/+7
| | | | llvm-svn: 151083
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-211-1/+3
| | | | | | | | | | | | | Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. llvm-svn: 151032
* Improve generated code for extending loads and some trunc stores on ARM.James Molloy2012-02-202-7/+140
| | | | | | Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. llvm-svn: 150956
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-199-53/+5
| | | | llvm-svn: 150918
* Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. ↵Craig Topper2012-02-191-4/+1
| | | | | | Remove unneeded 'using namespace'. llvm-svn: 150916
* Unify all shuffle mask checking functions take a mask and VT instead of ↵Craig Topper2012-02-191-85/+68
| | | | | | VectorShuffleSDNode. llvm-svn: 150913
* Make a bunch of X86ISelLowering shuffle functions static now that they are ↵Craig Topper2012-02-192-172/+51
| | | | | | no longer needed by isel. llvm-svn: 150908
* comment fix ARM.hJia Liu2012-02-191-1/+1
| | | | llvm-svn: 150904
* some comment fix for X86 and ARMJia Liu2012-02-198-8/+8
| | | | llvm-svn: 150902
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-194-20/+27
| | | | llvm-svn: 150899
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18293-384/+385
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Add X86InstrSVM.td that I forgot to add in r150873.Craig Topper2012-02-181-0/+62
| | | | llvm-svn: 150874
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-184-71/+61
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen2012-02-172-7/+9
| | | | llvm-svn: 150833
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