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* Print all the moves at a given label instead of just the first one.Rafael Espindola2011-04-261-9/+0
| | | | | | Remove previous DwarfCFI hack. llvm-svn: 130187
* Let dwarf writer allocate extra space in the debug location expression. This ↵Devang Patel2011-04-262-5/+8
| | | | | | space, if requested, will be used for complex addresses of the Blocks' variables. llvm-svn: 130178
* add a missed bitfield instcombine.Chris Lattner2011-04-251-0/+47
| | | | llvm-svn: 130137
* Lower BlockAddress node when relocation-model is static.Akira Hatanaka2011-04-252-16/+23
| | | | llvm-svn: 130131
* Remove some hard coded CR-LFs. Some of these were the entire files, one ofChandler Carruth2011-04-251-1/+1
| | | | | | | these was just one line of a file. Explicitly set the eol-style property on the files to try and ensure this fix stays. llvm-svn: 130125
* Fix comment typo. Noticed by Liu.Duncan Sands2011-04-251-1/+1
| | | | llvm-svn: 130120
* Fix Target/ARM/Thumb1FrameLowering.h header guard.Sebastian Redl2011-04-241-1/+1
| | | | llvm-svn: 130097
* Remove unused STL header includes.Jay Foad2011-04-232-4/+0
| | | | llvm-svn: 130068
* Silence an overzealous uninitialized variable warning from GCC.Benjamin Kramer2011-04-231-1/+1
| | | | llvm-svn: 130053
* Thumb2 and ARM add/subtract with carry fixes.Andrew Trick2011-04-234-115/+106
| | | | | | | | | | | | | Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
* whitespaceAndrew Trick2011-04-231-6/+6
| | | | llvm-svn: 130046
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+13
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-30/+1
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Add asserts.Devang Patel2011-04-221-0/+2
| | | | llvm-svn: 129995
* X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & ↵Benjamin Kramer2011-04-221-0/+75
| | | | | | | | | | | | | | | | | | | | | | | (C2 >> C1)) & C1. (Part of PR5039) This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is uint64_t foo(uint64_t x) { return (x&1) << 42; } which used to compile into bloated code: shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a] movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00] andq %rdi, %rax ## encoding: [0x48,0x21,0xf8] ret ## encoding: [0xc3] with this patch we can fold the immediate into the and: andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a] ret ## encoding: [0xc3] It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing that without making this code even more complicated. See the TODOs in the code. llvm-svn: 129990
* In Thumb2 mode, lower frame indix references to:Evan Cheng2011-04-222-9/+13
| | | | | | | | | | | add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 llvm-svn: 129971
* Compute the size of the FDE encoding instead of hard coding it. UpdateRafael Espindola2011-04-221-10/+1
| | | | | | X8664_ELFTargetObjectFile::getFDEEncoding to match reality. llvm-svn: 129959
* Remove unused argument.Rafael Espindola2011-04-211-6/+4
| | | | llvm-svn: 129955
* Fix DWARF description of Q registers.Devang Patel2011-04-211-0/+27
| | | | llvm-svn: 129952
* Fix DWARF description of S registers.Devang Patel2011-04-212-0/+44
| | | | llvm-svn: 129947
* As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF.Devang Patel2011-04-211-24/+32
| | | | llvm-svn: 129922
* PTX: Expand useable register spaceJustin Holewinski2011-04-211-6/+226
| | | | llvm-svn: 129913
* ptx: fix parameter orderingChe-Liang Chiou2011-04-211-4/+1
| | | | | | | | | This patch depends on the prior fix r129908 that changes to use std::find, rather than std::binary_search, on unordered array. Patch by Dan Bailey llvm-svn: 129909
* ptx: PTXMachineFunctionInfo no longer sort registers and so should not use ↵Che-Liang Chiou2011-04-211-2/+3
| | | | | | std::binary_search llvm-svn: 129908
* Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng2011-04-203-6/+4
| | | | llvm-svn: 129884
* Revert r129846; it's breaking a buildbot. SeeEli Friedman2011-04-201-0/+1
| | | | | | http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-checks/builds/825/steps/test.llvm.stage2/logs/st.ll llvm-svn: 129869
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-202-7/+16
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Excise unintended hunk in 129858. <rdar://problem/7662569>Stuart Hastings2011-04-201-5/+0
| | | | llvm-svn: 129862
* ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings2011-04-203-80/+173
| | | | | | <rdar://problem/7662569> llvm-svn: 129858
* PTX: Add intrinsics to list of built-in intrinsics, which allows them to beJustin Holewinski2011-04-209-24/+60
| | | | | | | | | | used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 llvm-svn: 129851
* ptx: add integer div and rem instructionChe-Liang Chiou2011-04-201-0/+2
| | | | | | Patched by Dan Bailey llvm-svn: 129848
* ptx: add floating-point comparison to setpChe-Liang Chiou2011-04-201-14/+234
| | | | | | Patched by Dan Bailey llvm-svn: 129847
* ptx: fix parameter orderingChe-Liang Chiou2011-04-201-1/+0
| | | | | | Patched by Dan Bailey llvm-svn: 129846
* This should always be signed chars, so use int8_t. This fixes a miscompile whenNick Lewycky2011-04-201-3/+3
| | | | | | | | llvm is built with unsigned chars where an immediate such as 0xff would be zero extended to 64-bits, turning "cmp $0xff,%eax" into "cmp $0xffffffffffffffff,%eax". llvm-svn: 129845
* Remove unused arguments.Rafael Espindola2011-04-201-3/+2
| | | | llvm-svn: 129844
* ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OSDaniel Dunbar2011-04-206-14/+15
| | | | | | triple component. llvm-svn: 129838
* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
| | | | llvm-svn: 129837
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-1910-99/+76
| | | | | | predicates. llvm-svn: 129816
* Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar2011-04-194-11/+7
| | | | llvm-svn: 129813
* Target/X86: Add getTargetTriple() accessor.Daniel Dunbar2011-04-191-0/+2
| | | | llvm-svn: 129812
* Target/PPC: Kill off DarwinVers, which is now dead.Daniel Dunbar2011-04-192-24/+1
| | | | llvm-svn: 129811
* Target/PPC: Eliminate a use of getDarwinVers().Daniel Dunbar2011-04-191-2/+4
| | | | llvm-svn: 129810
* Target/PPC: Add a TargetTriple field.Daniel Dunbar2011-04-192-1/+9
| | | | llvm-svn: 129809
* Target: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar2011-04-191-1/+8
| | | | llvm-svn: 129803
* Remove some duplicate op action entries and reorganize.Eric Christopher2011-04-191-8/+5
| | | | llvm-svn: 129781
* This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson2011-04-195-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. llvm-svn: 129775
* Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson2011-04-191-0/+2
| | | | llvm-svn: 129774
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-194-86/+182
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-192-0/+25
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* Some single-precision VFP instructions can execute in either the VPF or NeonBob Wilson2011-04-191-0/+24
| | | | | | pipelines, at least on Cortex-A9. llvm-svn: 129771
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