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* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-142-11/+14
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-2/+4
| | | | | | the alias". llvm-svn: 129485
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-132-8/+16
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-1/+1
| | | | llvm-svn: 129468
* Fix a regression caused by r102515 where explicit alignment on globals isCameron Zwarich2011-04-131-1/+1
| | | | | | | ignored. There was a test to catch this, but it was just blindly updated in a large change. This fixes another part of <rdar://problem/9275290>. llvm-svn: 129466
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Forgot to add this change for ↵Johnny Chen2011-04-131-4/+4
| | | | | | http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. llvm-svn: 129451
* Fix an obvious problem with an alignment computation. AsmPrinter actually doesCameron Zwarich2011-04-131-1/+1
| | | | | | | the max itself, so it is not easy to write a test case for this, but I added a test case that would fail if the code in AsmPrinter were removed. llvm-svn: 129432
* Fix a typo.Cameron Zwarich2011-04-132-7/+7
| | | | llvm-svn: 129429
* If a global variable has a specified alignment that is less than the preferredCameron Zwarich2011-04-131-2/+6
| | | | | | | alignment for its type, use the minimum of the specified alignment and the ABI alignment. This fixes <rdar://problem/9275290>. llvm-svn: 129428
* Reapply r129401 with patch for clang.Bill Wendling2011-04-132-31/+0
| | | | llvm-svn: 129419
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* Add @earlyclobber constraints to the writeback register of all ARM store ↵Jakob Stoklund Olesen2011-04-122-12/+24
| | | | | | | | | | instructions. The ARMARM specifies these instructions as unpredictable when storing the writeback register. This shouldn't affect code generation much since storing a pointer to itself is quite rare. llvm-svn: 129409
* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-122-0/+31
| | | | llvm-svn: 129403
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-122-31/+0
| | | | | | | | | Now that we have a first-class way to represent unaligned loads, the unaligned load intrinsics are superfluous. First part of <rdar://problem/8460511>. llvm-svn: 129401
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-122-6/+11
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-122-0/+5
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-122-0/+29
| | | | | | Ld/St Multiple. llvm-svn: 129365
* Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich2011-04-121-2/+22
| | | | | | | stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. llvm-svn: 129345
* A8.6.16 BJohnny Chen2011-04-121-0/+5
| | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-112-2/+14
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* Fix an error in the MBlaze delay slot filler.Wesley Peck2011-04-111-1/+1
| | | | llvm-svn: 129313
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-1116-228/+710
| | | | llvm-svn: 129311
* Don't crash on invalid instructions when disassembling MBlaze code.Wesley Peck2011-04-113-36/+115
| | | | | | This fixes http://llvm.org/bugs/show_bug.cgi?id=9653 llvm-svn: 129303
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-6/+17
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper ↵Owen Anderson2011-04-111-2/+5
| | | | | | use of the Commutable bit. llvm-svn: 129294
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
| | | | llvm-svn: 129288
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-111-0/+68
| | | | | | | | them as invalid instructions. llvm-svn: 129286
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-112-0/+2
| | | | llvm-svn: 129271
* Bugfix in the Cpp backend after API change on PHINode::Create.Nicolas Geoffray2011-04-101-1/+1
| | | | llvm-svn: 129248
* fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,Chris Lattner2011-04-092-0/+19
| | | | | | | InstAlias doesn't allow matching immediate operands, so we have to write C++ code to do this. llvm-svn: 129223
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | llvm-svn: 129160
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-082-23/+12
| | | | | | is lowered into a call to the specified trap function at sdisel time. llvm-svn: 129152
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | llvm-svn: 129148
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* Mark hasExtraDefRegAllocReq=1 on LDRD.Jim Grosbach2011-04-081-1/+5
| | | | | | | | | The previous cleanup of LDRD got overzealous and removed it, causing post-RA scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued. rdar://9244161 llvm-svn: 129144
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-074-5/+22
| | | | | | | | | | | | | with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. llvm-svn: 129110
* Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng2011-04-071-1/+23
| | | | | | instruction. rdar://9249183. llvm-svn: 129107
* Fix indentation.Akira Hatanaka2011-04-071-2/+2
| | | | llvm-svn: 129105
* Update ATUsed every time after expandRegLargeImmPair is called.Akira Hatanaka2011-04-071-4/+8
| | | | llvm-svn: 129104
* Fixed encoding for VEXTqfMon P Wang2011-04-071-2/+2
| | | | llvm-svn: 129101
* Fix handling of functions with internal linkage.Akira Hatanaka2011-04-071-8/+27
| | | | llvm-svn: 129099
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+5
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
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