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* Recommitting PALIGNR shift width fixes.Sean Callanan2009-11-201-8/+8
| | | | | | | Thanks to Daniel Dunbar for fixing clang intrinsics: http://llvm.org/viewvc/llvm-project?view=rev&revision=89499 llvm-svn: 89500
* Remove an incorrect overaggressive optimizationDale Johannesen2009-11-201-5/+3
| | | | | | (PPC specific). llvm-svn: 89496
* Reverting PALIGNR fix until I figure out how thisSean Callanan2009-11-201-8/+8
| | | | | | broke the Clang testsuite. llvm-svn: 89495
* Fixed PALIGNR to take 8-bit rotations in all cases.Sean Callanan2009-11-201-8/+8
| | | | | | | Also fixed the corresponding testcase, and the PALIGNR intrinsic (tested for correctness with llvm-gcc). llvm-svn: 89491
* Remat VLDRD from constpool. Clean up some instruction property specifications.Evan Cheng2009-11-204-9/+10
| | | | llvm-svn: 89478
* The verify() call of CPEIsInRange() isn't right for the assertion check ofJim Grosbach2009-11-201-2/+5
| | | | | | | | | | constant pool ranges, as CPEIsInRange() makes conservative assumptions about the potential alignment changes from branch adjustments. The verification, on the other hand, runs after those branch adjustments are made, so the effects on alignment are known and already taken into account. The sanity check in verify should check the range directly instead. llvm-svn: 89473
* Remove verifySizes() since it's not adding much value.Jim Grosbach2009-11-201-36/+0
| | | | llvm-svn: 89443
* Also CSE non-pic load from constant pools.Evan Cheng2009-11-201-1/+4
| | | | llvm-svn: 89440
* Fix codegen of conditional move of immediates. We were not making use of the ↵Evan Cheng2009-11-201-65/+127
| | | | | | immediate forms of cmov instructions at all. llvm-svn: 89423
* Update comment to reflect instruction.Eric Christopher2009-11-201-1/+1
| | | | llvm-svn: 89414
* When placing constant islands and adjusting for alignment padding, inlineJim Grosbach2009-11-191-7/+66
| | | | | | | | | | | assembly can confuse things utterly, as it's assumed that instructions in inline assembly are 4 bytes wide. For Thumb mode, that's often not true, so the calculations for when alignment padding will be present get thrown off, ultimately leading to out of range constant pool entry references. Making more conservative assumptions that padding may be necessary when inline asm is present avoids this situation. llvm-svn: 89403
* Refactor cmov selection code out to a separate function. No functionality ↵Evan Cheng2009-11-191-116/+122
| | | | | | change. llvm-svn: 89396
* Reverting the EH table patches.Bill Wendling2009-11-191-2/+2
| | | | | | | | | | | | | $ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk --- Reverse-merging r89279 into '.': U lib/CodeGen/AsmPrinter/DwarfException.cpp U lib/Target/TargetLoweringObjectFile.cpp $ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk --- Reverse-merging r89270 into '.': G lib/CodeGen/AsmPrinter/DwarfException.cpp G lib/Target/TargetLoweringObjectFile.cpp llvm-svn: 89379
* Added NLdStLN which is similar to NLdSt with the exception that op7_4 is notJohnny Chen2009-11-192-76/+169
| | | | | | | | fully specified at this level. Subclasses of NLdStLN can specify selective bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside ARMInstrNEON.td. llvm-svn: 89377
* fix typoJim Grosbach2009-11-191-1/+1
| | | | llvm-svn: 89369
* Fix a typo in a comment.Dan Gohman2009-11-191-1/+1
| | | | llvm-svn: 89360
* 80 col violation.Evan Cheng2009-11-191-1/+2
| | | | llvm-svn: 89337
* More consistent thumb1 asm printing.Evan Cheng2009-11-194-11/+27
| | | | llvm-svn: 89328
* Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.Evan Cheng2009-11-191-8/+26
| | | | llvm-svn: 89326
* Eliminate more * 4 in Thumb1 asm printing for consistency sake.Evan Cheng2009-11-191-4/+4
| | | | llvm-svn: 89325
* - Add sugregister logic to handle f64=(f32,f32).Bruno Cardoso Lopes2009-11-194-2/+166
| | | | | | | | | | | | - Support mips1 like load/store of doubles: Instead of: sdc $f0, X($3) Generate: swc $f0, X($3) swc $f1, X+4($3) llvm-svn: 89322
* Only use small sections for non linux targets!Bruno Cardoso Lopes2009-11-191-0/+7
| | | | llvm-svn: 89316
* The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EHBill Wendling2009-11-191-1/+1
| | | | | | exception table than DataRel. llvm-svn: 89279
* Add XCore support for indirectbr / blockaddress.Richard Osborne2009-11-184-1/+23
| | | | llvm-svn: 89273
* Attempt #2:Bill Wendling2009-11-181-1/+1
| | | | | | Place the EH table in the __TEXT section on MachO. It saves space. llvm-svn: 89270
* Added getDefaultSubtargetFeatures method to SubtargetFeatures class which ↵Viktor Kutuzov2009-11-181-0/+27
| | | | | | returns a correct feature string for given triple. llvm-svn: 89236
* Add ARMv6 itineraries.David Goodwin2009-11-183-13/+201
| | | | llvm-svn: 89218
* Fix a few places that were missed when we converted to unified syntax.Bob Wilson2009-11-181-2/+2
| | | | llvm-svn: 89214
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-184-0/+20
| | | | | | | | | contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. llvm-svn: 89187
* The llvm-gcc front-end and the pass manager use two separate TargetData objects.Bill Wendling2009-11-181-24/+116
| | | | | | | | | | | | | | | | | | This is probably not confined to *just* these two things. Anyway, the llvm-gcc front-end may look up the structure layout information for an abstract type. That information will be stored into a table with the FE's TD. Instruction combine can come along and also ask for information on that abstract type, but for a separate TD (the one associated with the pass manager). After the type is refined, the old structure layout information in the pass manager's TD file is out of date. If a new type is allocated in the same space as the old-unrefined type, then the structure type information in the pass manager's TD file will be wrong, but won't know it. Fix this by making the TD's structure type information an abstract type user. llvm-svn: 89176
* Enable arm jumpt table adjustment.Jim Grosbach2009-11-171-1/+1
| | | | llvm-svn: 89143
* Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6Anton Korobeynikov2009-11-171-5/+2
| | | | | | alignment imm (in the same way). Fix asmprinting for non-darwin platforms. llvm-svn: 89137
* Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm toJohnny Chen2009-11-171-0/+3
| | | | | | distinguish between them and the more generic instructions (add, mov, and ldr). llvm-svn: 89108
* Re-apply 89011. It's not to be blamed.Evan Cheng2009-11-172-4/+7
| | | | llvm-svn: 89081
* Revert 89011. Buildbot thinks it might be breaking stuff.Evan Cheng2009-11-172-7/+4
| | | | llvm-svn: 89076
* When moving a block for table jumps, make sure the prior block terminatorJim Grosbach2009-11-171-7/+9
| | | | | | | is analyzable so it can be updated. If it's not, be safe and don't move the block. llvm-svn: 89022
* MOV64rm should be marked isReMaterializable.Evan Cheng2009-11-171-1/+1
| | | | llvm-svn: 89019
* A few more instructions that should be marked re-materializable.Evan Cheng2009-11-172-4/+7
| | | | llvm-svn: 89011
* Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND toJohnny Chen2009-11-161-0/+2
| | | | | | | 0b1110 (ALways). This is so that the disassembler decoder can distinguish among BX_RET, BRIND, and BXr9. llvm-svn: 89000
* Make X86-64 in the Large model always emit 64-bit calls.Jeffrey Yasskin2009-11-164-39/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The large code model is documented at http://www.x86-64.org/documentation/abi.pdf and says that calls should assume their target doesn't live within the 32-bit pc-relative offset that fits in the call instruction. To do this, we turn off the global-address->target-global-address conversion in X86TargetLowering::LowerCall(). The first attempt at this broke the lazy JIT because it can separate the movabs(imm->reg) from the actual call instruction. The lazy JIT receives the address of the movabs as a relocation and needs to record the return address from the call; and then when that call happens, it needs to patch the movabs with the newly-compiled target. We could thread the call instruction into the relocation and record the movabs<->call mapping explicitly, but that seems to require at least as much new complication in the code generator as this change. To fix this, we make lazy functions _always_ go through a call stub. You'd think we'd only have to force lazy calls through a stub on difficult platforms, but that turns out to break indirect calls through a function pointer. The right fix for that is to distinguish between calls and address-of operations on uncompiled functions, but that's complex enough to leave for someone else to do. Another attempt at this defined a new CALL64i pseudo-instruction, which expanded to a 2-instruction sequence in the assembly output and was special-cased in the X86CodeEmitter's emitInstruction() function. That broke indirect calls in the same way as above. This patch also removes a hack forcing Darwin to the small code model. Without far-call-stubs, the small code model requires things of the JITMemoryManager that the DefaultJITMemoryManager can't provide. Thanks to echristo for lots of testing! llvm-svn: 88984
* - Check memoperand alignment instead of checking stack alignment. Most load ↵Evan Cheng2009-11-162-17/+14
| | | | | | | | / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
* Make the pass class name more explicit.Jim Grosbach2009-11-161-4/+6
| | | | llvm-svn: 88964
* make pass name a bit more clearJim Grosbach2009-11-161-1/+1
| | | | llvm-svn: 88961
* Simplify thumb2 jump table adjustments. Remove unnecessary calculation andJim Grosbach2009-11-161-58/+14
| | | | | | usage of block sizes and offsets. llvm-svn: 88935
* clarify commentJim Grosbach2009-11-161-2/+2
| | | | llvm-svn: 88933
* back off for a bit. tracking down weirdnessJim Grosbach2009-11-161-1/+1
| | | | llvm-svn: 88919
* Analyze has to be before checking the condition, obviously. Properly ↵Jim Grosbach2009-11-161-6/+8
| | | | | | construct an iterator for prior. llvm-svn: 88917
* Disable ldc1/sdc1 instructions for mips1 targets. Bruno Cardoso Lopes2009-11-161-1/+2
| | | | llvm-svn: 88887
* - Fix a small bug while handling target constant pools (one param was missing).Bruno Cardoso Lopes2009-11-162-1/+22
| | | | | | | | | | | | | | | - Add a smarter constant pool loading, instead of: lui $2, %hi($CPI1_0) addiu $2, $2, %lo($CPI1_0) lwc1 $f0, 0($2) Generate: lui $2, %hi($CPI1_0) lwc1 $f0, %lo($CPI1_0)($2) llvm-svn: 88886
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-154-2/+51
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
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