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* [SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions.Venkatraman Govindaraju2013-09-221-0/+4
| | | | llvm-svn: 191160
* [Sparc] Emit .register directive to declare the use of global registers %g2, ↵Venkatraman Govindaraju2013-09-221-0/+26
| | | | | | %g4, %g6 and %g7. llvm-svn: 191158
* Correct the pre-increment load latencies in the PPC A2 itineraryHal Finkel2013-09-221-3/+3
| | | | | | | | Pre-increment loads are microcoded on the A2, and the address increment occurs only after the load completes. As a result, the latency of the GPR address update is an additional 2 cycles on top of the load latency. llvm-svn: 191156
* [Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.Venkatraman Govindaraju2013-09-211-6/+6
| | | | llvm-svn: 191154
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-09-211-10/+1
| | | | | | | | splitting too." This reverts commit r191130. llvm-svn: 191138
* Remove alignment restrictions from FMA load folding.Craig Topper2013-09-211-31/+31
| | | | llvm-svn: 191136
* Fix the buildbotJuergen Ributzka2013-09-211-3/+3
| | | | llvm-svn: 191133
* [X86] Emulate AVX 256bit MIN/MAX support by splitting the vector.Juergen Ributzka2013-09-211-19/+45
| | | | | | | | | | | In AVX 256bit vectors are valid vectors and therefore the Type Legalizer doesn't split the VSELECT and SETCC nodes. AVX only supports MIN/MAX on 128bit vectors and this fix enables vector splitting for this special case in the X86 DAG Combiner. This fix is related to PR16695, PR17002, and <rdar://problem/14594431>. llvm-svn: 191131
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-09-211-1/+10
| | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask for the given target. This mask has usually te same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. llvm-svn: 191130
* Set .reorder for the stub so that gas takes care of delay slot processing.Reed Kotler2013-09-211-1/+3
| | | | llvm-svn: 191125
* [mips] MUL should clobber HI0 and LO0.Akira Hatanaka2013-09-201-0/+1
| | | | | | I cannot think of a test case that reliably triggers this bug. llvm-svn: 191109
* Lift alignment restrictions on load/store folding of VEXTRACTI128/VINSERTI128.Craig Topper2013-09-201-12/+12
| | | | llvm-svn: 191073
* Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-203-12/+26
| | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-192-2/+2
| | | | llvm-svn: 191052
* X86 horizontal vector reduction cost modelYi Jiang2013-09-191-0/+84
| | | | llvm-svn: 191021
* [NVPTX] Support constant vector globalsJustin Holewinski2013-09-191-1/+1
| | | | llvm-svn: 190997
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
| | | | llvm-svn: 190996
* X86: FrameIndex addressing modes do have a base register.Tim Northover2013-09-191-1/+2
| | | | | | | | | | | | | | When selecting the DAG (add (WrapperRIP ...), (FrameIndex ...)), X86 code had spotted the FrameIndex possibility and was working out whether it could fold the WrapperRIP into this. The test for forming a %rip version is notionally whether we already have a base or index register (%rip precludes both), but we were forgetting to account for the register that would be inserted later to access the frame. rdar://problem/15024520 llvm-svn: 190995
* Fix two issues regarding Got pointer (GP) setup.Reed Kotler2013-09-182-4/+14
| | | | | | | | | | | | | | | 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. llvm-svn: 190966
* More XCore TTI cleanup -- remove an unused private field flagged byChandler Carruth2013-09-181-4/+2
| | | | | | -Wunused-private-field with Clang. llvm-svn: 190941
* Target/XCore/CMakeLists.txt: Add XCoreTargetTransformInfo.cpp.NAKAMURA Takumi2013-09-181-0/+1
| | | | llvm-svn: 190937
* Prevent LoopVectorizer and SLPVectorizer running if the target has no vector ↵Robert Lytton2013-09-184-0/+97
| | | | | | | | | | registers. XCore target: Add XCoreTargetTransformInfo This is where getNumberOfRegisters() resides, which in turn returns the number of vector registers (=0). llvm-svn: 190936
* [SystemZ] Add unsigned compare-and-branch instructionsRichard Sandiford2013-09-185-2/+75
| | | | | | | | | | | | | | | For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. llvm-svn: 190930
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-183-1/+80
| | | | | | Patch by Bradley Smith! llvm-svn: 190928
* Prevent extra calls to ToggleFeature for Feature64Bit and FeatureCMOV if ↵Craig Topper2013-09-181-2/+2
| | | | | | they've already been enabled. The extra call ends up clearing the bit in FeatureBits since its a 'toggle'. Can't prove that anything was broken because of this since I don't think the FeatureBits for these are used. llvm-svn: 190920
* Fix X86 subtarget to not overwrite the autodetected features by calling ↵Craig Topper2013-09-181-1/+1
| | | | | | InitMCProcessorInfo right after detecting them. Instead add a new function that only updates the scheduling model and call that. llvm-svn: 190919
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-181-10/+10
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. llvm-svn: 190916
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-171-0/+20
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 llvm-svn: 190898
* [PowerPC] Add a FIXME.Bill Schmidt2013-09-171-0/+4
| | | | | | | | Documenting a design choice to generate only medium model sequences for TLS addresses at this time. Small and large code models could be supported if necessary. llvm-svn: 190883
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-172-8/+22
| | | | | | | | | | | | | | Large code model on PPC64 requires creating and referencing TOC entries when using the addis/ld form of addressing. This was not being done in all cases. The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two test cases are also modified to reflect this requirement. Fast-isel was not creating correct code for loading floating-point constants using large code model. This also requires the addis/ld form of addressing. Previously we were using the addis/lfd shortcut which is only applicable to medium code model. One test case is modified to reflect this requirement. llvm-svn: 190882
* Remove unused code, which had been commented out.Preston Gurd2013-09-171-5/+0
| | | | llvm-svn: 190869
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-171-14/+26
| | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. llvm-svn: 190864
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-172-9/+27
| | | | llvm-svn: 190862
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-171-3070/+3070
| | | | llvm-svn: 190851
* Add AES and SHA instructions to the load folding tables.Craig Topper2013-09-171-0/+25
| | | | llvm-svn: 190850
* Fix column alignment. No functional change.Craig Topper2013-09-171-4/+4
| | | | llvm-svn: 190849
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-175-14/+468
| | | | llvm-svn: 190839
* [PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.Bill Schmidt2013-09-161-1/+8
| | | | | | | | | Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which is a nop on PPC64. This is needed to keep the register class system happy, but on the fast-isel path it is not removed before emit as it is for DAG select. Ignore this op when emitting instructions. llvm-svn: 190795
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-163-1/+60
| | | | | | Test cases are added. llvm-svn: 190780
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-162-47/+36
| | | | llvm-svn: 190779
* [SystemZ] Improve extload handlingRichard Sandiford2013-09-162-74/+92
| | | | | | | | | | | | The port originally had special patterns for extload, mapping them to the same instructions as sextload. It seemed neater to have patterns that match "an extension that is allowed to be signed" and "an extension that is allowed to be unsigned". This was originally meant to be a clean-up, but it does improve the handling of promoted integers a little, as shown by args-06.ll. llvm-svn: 190777
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-162-2/+3
| | | | llvm-svn: 190775
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-1/+2
| | | | | | | | | | | | | | | | | | | This is a re-commit of r190764, with an extra check to make sure that we're not performing the transformation on illegal types (a small test case has been added for this as well). Original commit message: The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190771
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-153-5/+5
| | | | llvm-svn: 190770
* Revert r190764: PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-0/+1
| | | | | | | | | | | | | | | | | This is causing test-suite failures. Original commit message: The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190765
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-1/+0
| | | | | | | | | | | | | The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190764
* Expand the mask capability for deciding which functions are mips16 and mips32Reed Kotler2013-09-151-2/+3
| | | | | | | so it can be better used for general interoperability testing between mips32 and mips16. llvm-svn: 190762
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-141-0/+27
| | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
| | | | llvm-svn: 190749
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-142-2/+2
| | | | llvm-svn: 190746
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