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* AArch64/ARM64: produce more informative diagnostic assembling some immediatesTim Northover2014-05-062-32/+38
| | | | | | | No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-061-37/+46
| | | | llvm-svn: 208076
* [ARM64] Enable alignment control option in front-end for ARM64.Kevin Qin2014-05-061-4/+15
| | | | | | This is the modification in llvm part. llvm-svn: 208074
* Use X86 memory operand enums instead of hardcoding.Craig Topper2014-05-061-16/+20
| | | | llvm-svn: 208064
* Fix i128 div/mod on mingw64Reid Kleckner2014-05-062-0/+72
| | | | | | | | | | The Win64 docs are very clear that anything larger than 8 bytes is passed by reference, and GCC MinGW64 honors that for __modti3 and friends. Patch by Jameson Nash! llvm-svn: 208029
* Fix typo.Eric Christopher2014-05-051-1/+1
| | | | llvm-svn: 208006
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-0/+1
| | | | llvm-svn: 208005
* Revert "Optimize shufflevector that copies an i64/f64 and zeros the rest."Filipe Cabecinhas2014-05-051-21/+12
| | | | | | This reverts commit 207992. I misread the phab number on the LGTM. llvm-svn: 207993
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-051-12/+21
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 207992
* R600/SI: allow 5 more input SGPRs to a shaderMarek Olsak2014-05-051-1/+1
| | | | | | | Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs). Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 207990
* CodeGen: correct memset emittance for WoASaleem Abdulrasool2014-05-041-1/+2
| | | | | | | | Windows on ARM does not conform to AEABI. However, memset would be emitted using the AEABI signature, resulting in inverted parameters. Handle this special case appropriately. llvm-svn: 207943
* MC: support FK_SecRel_4 for Windows on ARMSaleem Abdulrasool2014-05-042-0/+7
| | | | | | | | | Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. llvm-svn: 207941
* AVX-512: minor change in rndscale intrinsicElena Demikhovsky2014-05-041-2/+11
| | | | llvm-svn: 207937
* X86: further range-loopify AsmPrinterSaleem Abdulrasool2014-05-041-18/+16
| | | | | | Use more range loops in the X86AsmPrinter. NFC. llvm-svn: 207928
* X86: remove X86COFFMachineModuleInfoSaleem Abdulrasool2014-05-044-82/+0
| | | | | | Remove dead code. This is vestigial after r98384. llvm-svn: 207927
* X86: repair export compatibility with MinGW/cygwinSaleem Abdulrasool2014-05-041-1/+6
| | | | | | | | | | | | | | Both MinGW and cygwin (i686) construct export directives without the global leader prefix. This is mostly due to the fact that they use GNU ld which does not correctly handle the export directive. This apparently has been been broken for a while. However, this was recently reported as being broken by mingwandroid and diorcety of the msys2 project. Remove the global leader prefix if targeting MinGW or cygwin, otherwise, retain the global leader prefix. Add an explicit test for cygwin's behaviour of export directives. llvm-svn: 207926
* X86: refactor export directive generationSaleem Abdulrasool2014-05-042-22/+27
| | | | | | | | | Create a helper function to generate the export directive. This was previously duplicated inline to handle export directives for variables and functions. This also enables the use of range-based iterators for the generation of the directive rather than the traditional loops. NFC. llvm-svn: 207925
* Fix pr19645.Rafael Espindola2014-05-034-6/+7
| | | | | | | | | | | | | | | | The fix itself is fairly simple: move getAccessVariant to MCValue so that we replace the old weak expression evaluation with the far more general EvaluateAsRelocatable. This then requires that EvaluateAsRelocatable stop when it finds a non trivial reference kind. And that in turn requires the ELF writer to look harder for weak references. Last but not least, this found a case where we were being bug by bug compatible with gas and accepting an invalid input. I reported pr19647 to track it. llvm-svn: 207920
* [ARM64] Correctly select ANDWri in FastISel.Joey Gouly2014-05-031-6/+13
| | | | | | http://reviews.llvm.org/D3598 llvm-svn: 207917
* Add a description for AMD's bdver4 (aka Excavator).Benjamin Kramer2014-05-021-0/+7
| | | | | | This is just bdver3 + AVX2 + BMI2. llvm-svn: 207847
* R600/SI: Add processor type for Mullins.Tom Stellard2014-05-021-0/+2
| | | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 207846
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
| | | | llvm-svn: 207844
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-027-36/+231
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* AArch64/ARM64: add patterns for post-indexed ST1 ops.Tim Northover2014-05-021-0/+47
| | | | llvm-svn: 207840
* ARM64: refactor NEON post-indexed loads & stores (MC).Tim Northover2014-05-023-987/+443
| | | | | | | | | | | | | | | | | | | Previously, LLVM had no knowledge that these instructions actually modified their address register: fine if they never end up in CodeGen, but when I'd rather like to write some patterns for them it becomes a disaster. The change is mostly straightforward, I think the most significant design decision was to *always* put the address write-back first. This allows loads and stores to be accessed more uniformly, for example permitting the continued sharing of the InstAlias definitions. I also discovered that the custom Decode logic is no longer needed, so I removed it. No tests, because there should be no functionality change. llvm-svn: 207839
* AArch64/ARM64: support indexed loads/stores on vector types.Tim Northover2014-05-024-1/+72
| | | | | | | | While post-indexed LD1/ST1 instructions do exist for vector loads, this patch makes use of the more flexible addressing-modes in LDR/STR instructions. llvm-svn: 207838
* Remove HexagonTargetMachine::addPassesForOptimizations; it is not needed any ↵Pranav Bhandarkar2014-05-012-16/+0
| | | | | | more. llvm-svn: 207800
* Add basic functionality for assignment of ints.Reed Kotler2014-05-011-1/+167
| | | | | | | | | | | | | | | This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel Test Plan: simplestore.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3527 llvm-svn: 207790
* Add an optimization that does CSE in a group of similar GEPs.Eli Bendersky2014-05-011-4/+17
| | | | | | | | | | | | | | This optimization merges the common part of a group of GEPs, so we can compute each pointer address by adding a simple offset to the common part. The optimization is currently only enabled for the NVPTX backend, where it has a large payoff on some benchmarks. Review: http://reviews.llvm.org/D3462 Patch by Jingyue Wu. llvm-svn: 207783
* R600/SI: Fix verifier error with pseudo store instructions.Matt Arsenault2014-05-011-1/+1
| | | | | | | | Use i32 instead of specifying SReg_32. When this is the pseudo INDIRECT_BASE_ADDR, this would give a bogus verifier error. llvm-svn: 207770
* [ARM64] Prefer generation of bzero on Darwin onlyBradley Smith2014-05-011-2/+5
| | | | llvm-svn: 207760
* Don't force symbols to be globals in .thumb_set.Rafael Espindola2014-05-011-5/+2
| | | | | | | | | | | | | | | | | | | | | | We currently force symbols to be globals in .thumb_set. The intent seems to be that given .thumb_set foo, bar we emit an undefined symbol to bar if it is never defined. The side effect is that we mark bar as global, even if it is defined, which gas does not. Producing an undefined reference to bar is a general difference from MC and gas. For example, given a = b gas will produce an undefined reference to b, MC will not. I would be surprised if any code depends on this, but it it does, we should fix the general difference, not special case .thumb_set. llvm-svn: 207757
* AArch64/ARM64: print BFM instructions as BFI or BFXILTim Northover2014-05-011-0/+27
| | | | | | | The canonical form of the BFM instruction is always one of the more explicit extract or insert operations, which makes reading output much easier. llvm-svn: 207752
* Correction to assert statemtent to allow 32-bit unsigned numbers with the ↵Richard Barton2014-05-011-2/+2
| | | | | | | | top bit set. This fixes an ARM assembler crash - regression test added. llvm-svn: 207747
* [ARM64] Conditionalize CPU specific system registers on subtarget featuresBradley Smith2014-05-015-18/+74
| | | | llvm-svn: 207742
* [mips] Move expansion of .cpsetup to target streamer.Matheus Almeida2014-05-013-51/+80
| | | | | | | | | | | | | | | Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
* [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, ↵Daniel Sanders2014-05-011-3/+1
| | | | | | | | | | and drotrv GAS doesn't actually accept these particular cases. The mnemonic without the trailing 'v' still supports two-operand aliases. llvm-svn: 207740
* ARM: fix memory leak, simplify WoA stack probingSaleem Abdulrasool2014-05-011-9/+3
| | | | | | | | | This fixes the memory leak introduced with the initial addition of support for WoA stack probing. Now that the pseudo-instruction expansion can handle an external symbol, use that to generate the load which simplifies the logic as well as avoids the memory leak. llvm-svn: 207737
* ARM: support expanding external symbols in 32-bit movesSaleem Abdulrasool2014-05-011-2/+14
| | | | | | | | This enhances the expansion of the mov32imm pseudo-instruction to support an external symbol reference. This is motivated by a simplification of the stack probe emission for Windows on ARM (and fixing a leak). llvm-svn: 207736
* If necessary for indirect encodings, emit stubs.Joerg Sonnenberger2014-05-011-0/+22
| | | | llvm-svn: 207730
* Prepare support of Itanium ABI on ARM as opposed to EHABI byJoerg Sonnenberger2014-04-301-13/+16
| | | | | | conditionally emitting .fnstart and friends only for EHABI. llvm-svn: 207718
* Restore condition incorrectly changed in r96289 to the older state.Joerg Sonnenberger2014-04-301-1/+1
| | | | llvm-svn: 207716
* [ARM64] Prevent bit extraction to be adjusted by following shiftWeiming Zhao2014-04-302-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | For pattern like ((x >> C1) & Mask) << C2, DAG combiner may convert it into (x >> (C1-C2)) & (Mask << C2), which makes pattern matching of ubfx more difficult. For example: Given %shr = lshr i64 %x, 4 %and = and i64 %shr, 15 %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, %i64 2, i64 %and %0 = load i64* %arrayidx With current shift folding, it takes 3 instrs to compute base address: lsr x8, x0, #1 and x8, x8, #0x78 add x8, x9, x8 If using ubfx, it only needs 2 instrs: ubfx x8, x0, #4, #4 add x8, x9, x8, lsl #3 This fixes bug 19589 llvm-svn: 207702
* [X86] Never hoist the shift value of a shift instruction.Michael Zolotukhin2014-04-301-3/+7
| | | | | | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. This change is like r206101, but for X86. rdar://problem/16190769 llvm-svn: 207692
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 llvm-svn: 207673
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 llvm-svn: 207671
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-301-6/+4
| | | | llvm-svn: 207669
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-305-18/+34
| | | | llvm-svn: 207668
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-302-1/+9
| | | | llvm-svn: 207667
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