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* [ARM] Combine base-updating/post-incrementing vector load/stores.Ahmed Bougacha2014-12-101-6/+38
| | | | | | | | | | | | | | | | | | We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 llvm-svn: 223862
* [Hexagon] [NFC] Cleaning up unused classes.Colin LeMahieu2014-12-091-30/+0
| | | | llvm-svn: 223845
* [ARM] Factor out base-updating VLD/VST combiner function. NFC.Ahmed Bougacha2014-12-091-6/+15
| | | | | | | | | Move the combiner-state check into another function, add a few small comments, and use a more general type in a cast<>. In preparation for a future patch. llvm-svn: 223834
* [ARM] Move the store combiner function down. NFC.Ahmed Bougacha2014-12-091-141/+143
| | | | | | | And flip its final condition. In preparation for a future patch. llvm-svn: 223833
* [ARM] Also support v2f64 vld1/vst1.Ahmed Bougacha2014-12-091-0/+2
| | | | | | | | | It was missing from the VLD1/VST1 handling logic, even though the corresponding instructions exist (same form as v2i64). In preparation for a future patch. llvm-svn: 223832
* [Hexagon] Fixing broken tests.Colin LeMahieu2014-12-091-1/+2
| | | | llvm-svn: 223823
* [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.Colin LeMahieu2014-12-099-178/+194
| | | | llvm-svn: 223821
* [FastISel][AArch64] Fix a missing nullptr check in 'computeAddress'.Juergen Ributzka2014-12-091-1/+1
| | | | | | | | | The load/store value type is currently not available when lowering the memcpy intrinsic. Add the missing nullptr check to support this in 'computeAddress'. Fixes rdar://problem/19178947. llvm-svn: 223818
* [Hexagon] Adding word combine dot-new form and replacing old combine opcode.Colin LeMahieu2014-12-095-80/+51
| | | | llvm-svn: 223815
* [AVX512] Added lowering for VBROADCASTSS/SD instructions.Robert Khasanov2014-12-092-1/+56
| | | | | | | Lowering patterns were written through avx512_broadcast_pat multiclass as pattern generates VBROADCAST and COPY_TO_REGCLASS nodes. Added lowering tests. llvm-svn: 223804
* IR: Split Metadata from ValueDuncan P. N. Exon Smith2014-12-093-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split `Metadata` away from the `Value` class hierarchy, as part of PR21532. Assembly and bitcode changes are in the wings, but this is the bulk of the change for the IR C++ API. I have a follow-up patch prepared for `clang`. If this breaks other sub-projects, I apologize in advance :(. Help me compile it on Darwin I'll try to fix it. FWIW, the errors should be easy to fix, so it may be simpler to just fix it yourself. This breaks the build for all metadata-related code that's out-of-tree. Rest assured the transition is mechanical and the compiler should catch almost all of the problems. Here's a quick guide for updating your code: - `Metadata` is the root of a class hierarchy with three main classes: `MDNode`, `MDString`, and `ValueAsMetadata`. It is distinct from the `Value` class hierarchy. It is typeless -- i.e., instances do *not* have a `Type`. - `MDNode`'s operands are all `Metadata *` (instead of `Value *`). - `TrackingVH<MDNode>` and `WeakVH` referring to metadata can be replaced with `TrackingMDNodeRef` and `TrackingMDRef`, respectively. If you're referring solely to resolved `MDNode`s -- post graph construction -- just use `MDNode*`. - `MDNode` (and the rest of `Metadata`) have only limited support for `replaceAllUsesWith()`. As long as an `MDNode` is pointing at a forward declaration -- the result of `MDNode::getTemporary()` -- it maintains a side map of its uses and can RAUW itself. Once the forward declarations are fully resolved RAUW support is dropped on the ground. This means that uniquing collisions on changing operands cause nodes to become "distinct". (This already happened fairly commonly, whenever an operand went to null.) If you're constructing complex (non self-reference) `MDNode` cycles, you need to call `MDNode::resolveCycles()` on each node (or on a top-level node that somehow references all of the nodes). Also, don't do that. Metadata cycles (and the RAUW machinery needed to construct them) are expensive. - An `MDNode` can only refer to a `Constant` through a bridge called `ConstantAsMetadata` (one of the subclasses of `ValueAsMetadata`). As a side effect, accessing an operand of an `MDNode` that is known to be, e.g., `ConstantInt`, takes three steps: first, cast from `Metadata` to `ConstantAsMetadata`; second, extract the `Constant`; third, cast down to `ConstantInt`. The eventual goal is to introduce `MDInt`/`MDFloat`/etc. and have metadata schema owners transition away from using `Constant`s when the type isn't important (and they don't care about referring to `GlobalValue`s). In the meantime, I've added transitional API to the `mdconst` namespace that matches semantics with the old code, in order to avoid adding the error-prone three-step equivalent to every call site. If your old code was: MDNode *N = foo(); bar(isa <ConstantInt>(N->getOperand(0))); baz(cast <ConstantInt>(N->getOperand(1))); bak(cast_or_null <ConstantInt>(N->getOperand(2))); bat(dyn_cast <ConstantInt>(N->getOperand(3))); bay(dyn_cast_or_null<ConstantInt>(N->getOperand(4))); you can trivially match its semantics with: MDNode *N = foo(); bar(mdconst::hasa <ConstantInt>(N->getOperand(0))); baz(mdconst::extract <ConstantInt>(N->getOperand(1))); bak(mdconst::extract_or_null <ConstantInt>(N->getOperand(2))); bat(mdconst::dyn_extract <ConstantInt>(N->getOperand(3))); bay(mdconst::dyn_extract_or_null<ConstantInt>(N->getOperand(4))); and when you transition your metadata schema to `MDInt`: MDNode *N = foo(); bar(isa <MDInt>(N->getOperand(0))); baz(cast <MDInt>(N->getOperand(1))); bak(cast_or_null <MDInt>(N->getOperand(2))); bat(dyn_cast <MDInt>(N->getOperand(3))); bay(dyn_cast_or_null<MDInt>(N->getOperand(4))); - A `CallInst` -- specifically, intrinsic instructions -- can refer to metadata through a bridge called `MetadataAsValue`. This is a subclass of `Value` where `getType()->isMetadataTy()`. `MetadataAsValue` is the *only* class that can legally refer to a `LocalAsMetadata`, which is a bridged form of non-`Constant` values like `Argument` and `Instruction`. It can also refer to any other `Metadata` subclass. (I'll break all your testcases in a follow-up commit, when I propagate this change to assembly.) llvm-svn: 223802
* [Hexagon] Updating predicate register transfers and adding tstbit to allow ↵Colin LeMahieu2014-12-095-27/+74
| | | | | | select selection. Updating ll tests with predicate transfers that previously had nop encodings. llvm-svn: 223800
* [PowerPC 4/4] Enable little-endian support for VSX.Bill Schmidt2014-12-091-7/+0
| | | | | | | | With the foregoing three patches, VSX instructions can be used for little endian. This patch removes the restriction that prevented this, and re-enables the test cases from the first three patches. llvm-svn: 223792
* [PowerPC 3/4] Little-endian adjustments for VSX vector shuffleBill Schmidt2014-12-091-0/+9
| | | | | | | | | | | | | | | | When performing instruction selection for ISD::VECTOR_SHUFFLE, there is special code for handling v2f64 and v2i64 using VSX instructions. This code must be adjusted for little-endian. Because the two inputs are treated as a double-wide register, we must swap their order for little endian. To get the appropriate mask elements to use with the big-endian biased XXPERMDI instruction, we must reverse their order and invert the bits. A new test is added to test the 16 possible values of the shuffle mask. It is initially disabled for reasons specified in the test. It is re-enabled by patch 4/4. llvm-svn: 223791
* [PowerPC 2/4] Little-endian adjustments for VSX insert/extract operationsBill Schmidt2014-12-091-0/+14
| | | | | | | | | | | | | | | | | | | For little endian, we need to make some straightforward adjustments in the code expansions for scalar_to_vector and vector_extract of v2f64. First, scalar_to_vector must place the scalar into vector element zero. However, our implementation of SUBREG_TO_REG will place it into big-element vector element zero (high-order bits), and for little endian we need it in the low-order bits. The LE implementation splats the high-order doubleword into the low-order doubleword. Second, the meaning of (vector_extract x, 0) and (vector_extract x, 1) must be reversed for similar reasons. A new test is added that tests code generation for insertelement and extractelement for both element 0 and element 1. It is disabled in this patch but enabled in patch 4/4, for reasons stated in the test. llvm-svn: 223788
* [AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from ↵Robert Khasanov2014-12-091-23/+33
| | | | | | | | | General Purpose Register) encodings for AVX512-BW/VL subsets Added encoding tests. llvm-svn: 223787
* [PowerPC 1/4] Little-endian adjustments for VSX loads/storesBill Schmidt2014-12-093-2/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses the inherent big-endian bias in the lxvd2x, lxvw4x, stxvd2x, and stxvw4x instructions. These instructions load vector elements into registers left-to-right (with the first element loaded into the high-order bits of the register), regardless of the endian setting of the processor. However, these are the only vector memory instructions that permit unaligned storage accesses, so we want to use them for little-endian. To make this work, a lxvd2x or lxvw4x is replaced with an lxvd2x followed by an xxswapd, which swaps the doublewords. This works for lxvw4x as well as lxvd2x, because for lxvw4x on an LE system the vector elements are in LE order (right-to-left) within each doubleword. (Thus after lxvw2x of a <4 x float> the elements will appear as 1, 0, 3, 2. Following the swap, they will appear as 3, 2, 0, 1, as desired.) For stores, an stxvd2x or stxvw4x is replaced with an stxvd2x preceded by an xxswapd. Introduction of extra swap instructions provides correctness, but obviously is not ideal from a performance perspective. Future patches will address this with optimizations to remove most of the introduced swaps, which have proven effective in other implementations. The introduction of the swaps is performed during lowering of LOAD, STORE, INTRINSIC_W_CHAIN, and INTRINSIC_VOID operations. The latter are used to translate intrinsics that specify the VSX loads and stores directly into equivalent sequences for little endian. Thus code that uses vec_vsx_ld and vec_vsx_st does not have to be modified to be ported from BE to LE. We introduce new PPCISD opcodes for LXVD2X, STXVD2X, and XXSWAPD for use during this lowering step. In PPCInstrVSX.td, we add new SDType and SDNode definitions for these (PPClxvd2x, PPCstxvd2x, PPCxxswapd). These are recognized during instruction selection and mapped to the correct instructions. Several tests that were written to use -mcpu=pwr7 or pwr8 are modified to disable VSX on LE variants because code generation changes with this and subsequent patches in this set. I chose to include all of these in the first patch than try to rigorously sort out which tests were broken by one or another of the patches. Sorry about that. The new test vsx-ldst-builtin-le.ll, and the changes to vsx-ldst.ll, are disabled until LE support is enabled because of breakages that occur as noted in those tests. They are re-enabled in patch 4/4. llvm-svn: 223783
* [x86] Fix the test to actually test things for the CPU names, add theChandler Carruth2014-12-091-0/+4
| | | | | | | | | | | | | missing barcelona CPU which that test uncovered, and remove the 32-bit x86 CPUs which I really wasn't prepared to audit and test thoroughly. If anyone wants to clean up the 32-bit only x86 CPUs, go for it. Also, if anyone else wants to try to de-duplicate the AMD CPUs, that'd be cool, but from the looks of it wouldn't save as much as it did for the Intel CPUs. llvm-svn: 223774
* Removing an unused variable to silence a -Wunused-but-set-variable warning. NFC.Aaron Ballman2014-12-091-2/+0
| | | | llvm-svn: 223773
* Fix modified immediate bug reported by MC Hammer.Asiri Rathnayake2014-12-091-11/+6
| | | | | | | | | | | | | Instructions of the form [ADD Rd, pc, #imm] are manually aliased in processInstruction() to use ADR. To accomodate this, mod_imm handling had to be tweaked a bit. Turns out it was the manual aliasing that must be tweaked to accommodate mod_imms instead. More information about the parsed instruction is available at the point where processInstruction() is invoked, which makes it easier to detect a mod_imm at that point rather than trying to detect a potential alias when a mod_imm is being prepped. Added a test case and fixed some white spaces as well. llvm-svn: 223772
* [x86] Bring some sanity to the x86 CPU processor definitions.Chandler Carruth2014-12-091-61/+139
| | | | | | | | | | | | | | | | | | Notably, this adds simple micro-architecture names for the Intel CPU variants, and defines the old 'core'-based names as aliases. GCC has started to simplify their documented interface to use these names as well, so it seems like we can start to converge on a consistent pattern. I'd appreciate Intel double checking the entries that aren't yet documented widely, especially Atom (Bonnell and Silvermont), Knights Landing, and Skylake. But this change shouldn't break any existing users. Also, ran clang-format to re-format this code and it actually worked (modulo a tiny bug) so hopefully we can start to stop thinking about formatting this stuff. llvm-svn: 223769
* AVX-512: Added some comments to ERI scalar intrinsics.Elena Demikhovsky2014-12-092-6/+17
| | | | | | No functional change. llvm-svn: 223761
* test commit (spelling correction)Mohit K. Bhakkad2014-12-091-1/+1
| | | | llvm-svn: 223758
* [X86] Convert esp-relative movs of function arguments into pushes, step 1Michael Kuperstein2014-12-092-4/+125
| | | | | | | | | | | This handles the simplest case for mov -> push conversion: 1. x86-32 calling convention, everything is passed through the stack. 2. There is no reserved call frame. 3. Only registers or immediates are pushed, no attempt to combine a mem-reg-mem sequence into a single PUSHmm. Differential Revision: http://reviews.llvm.org/D6503 llvm-svn: 223757
* Restore r223709 as it was meant to be, and enable FeatureP8Vector for P8Bill Schmidt2014-12-091-2/+2
| | | | llvm-svn: 223751
* Revert r223709, "[PowerPC]Activate FeatureVSX for the Power target", to ↵NAKAMURA Takumi2014-12-091-3/+5
| | | | | | | | | | | | | | | | | | | unbreak bots. CodeGen/PowerPC/vsx-p8.ll was failing. '+power8-vector' is not a recognized feature for this target (ignoring feature) llvm/test/CodeGen/PowerPC/vsx-p8.ll:33:14: error: expected string not found in input ; CHECK-REG: lxvw4x 34, 0, 3 ^ <stdin>:50:2: note: scanning from here .align 3 ^ <stdin>:61:2: note: possible intended match here lvx 3, 0, 3 ^ llvm-svn: 223729
* R600/SI: Set MayStore = 0 on MUBUF loadsTom Stellard2014-12-091-1/+1
| | | | llvm-svn: 223722
* R600/SI: Move setting of the lds bit to the base MUBUF classTom Stellard2014-12-091-6/+9
| | | | llvm-svn: 223721
* [Hexagon] Removing old def versions and replacing usages with versions that ↵Colin LeMahieu2014-12-085-182/+40
| | | | | | have encodings. llvm-svn: 223720
* [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register ↵Colin LeMahieu2014-12-081-0/+84
| | | | | | forms, mask, and vitpack instructions and patterns. llvm-svn: 223710
* [PowerPC]Activate FeatureVSX for the Power targetBill Seurer2014-12-081-5/+3
| | | | | | | | This change activates FeatureVSX for Power 7 and Power 8 in PPC.td. http://reviews.llvm.org/D6570 llvm-svn: 223709
* [PowerPC] Don't use a non-allocatable register to implement the 'cc' aliasHal Finkel2014-12-082-9/+6
| | | | | | | | | | | | | | | | GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when processing inline asm constraints. This had previously been implemented using a non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but the infrastructure does not seem to support this properly (neither the register allocator nor the scheduler properly accounts for the alias). Instead, we can just process this as a naming alias inside of the inline asm constraint-processing code, so we'll do that instead. There are two regression tests, one where the post-RA scheduler did the wrong thing with the non-allocatable alias, and one where the register allocator did the wrong thing. Fixes PR21742. llvm-svn: 223708
* [Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.Colin LeMahieu2014-12-081-46/+50
| | | | llvm-svn: 223702
* [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.Colin LeMahieu2014-12-082-32/+50
| | | | llvm-svn: 223701
* [Hexagon] Adding xtype parity, min, minu, max, maxu instructions.Colin LeMahieu2014-12-084-0/+110
| | | | llvm-svn: 223693
* [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.Colin LeMahieu2014-12-081-2/+102
| | | | llvm-svn: 223692
* R600/SI: Move continue after checking s_mov_b32.Matt Arsenault2014-12-081-3/+3
| | | | | | There's nothing else to bother trying to shrink these. llvm-svn: 223686
* [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up ↵Colin LeMahieu2014-12-082-16/+22
| | | | | | shift patterns. llvm-svn: 223680
* [CompactUnwind] Fix register encoding logicBruno Cardoso Lopes2014-12-081-1/+1
| | | | | | | | | | | | Fix a compact unwind encoding logic bug which would try to encode more callee saved registers than it should, leading to early bail out in the encoding logic and abusive use of DWARF frame mode unnecessarily. Also remove no-compact-unwind.ll which was testing the wrong thing based on this bug and move it to valid 'compact unwind' tests. Added other few more tests too. llvm-svn: 223676
* AArch64: treat HFAs containing "half" types as blocks too.Tim Northover2014-12-081-0/+5
| | | | llvm-svn: 223669
* [X86] Improved tablegen patters for matching TZCNT/LZCNT.Andrea Di Biagio2014-12-081-24/+29
| | | | | | | | | | | Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
* [Hexagon] Adding combine reg, reg with predicated forms.Colin LeMahieu2014-12-081-0/+7
| | | | llvm-svn: 223667
* [Hexagon] Adding packhl instruction.Colin LeMahieu2014-12-081-0/+6
| | | | llvm-svn: 223664
* [mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.Daniel Sanders2014-12-081-13/+28
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6213 llvm-svn: 223662
* [X86] Improved lowering of packed v8i16 vector shifts by non-constant count.Andrea Di Biagio2014-12-081-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch, the backend sub-optimally expanded the non-constant shift count of a v8i16 shift into a sequence of two 'movd' plus 'movzwl'. With this patch the backend checks if the target features sse4.1. If so, then it lets the shuffle legalizer deal with the expansion of the shift amount. Example: ;; define <8 x i16> @test(<8 x i16> %A, <8 x i16> %B) { %shamt = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer %shl = shl <8 x i16> %A, %shamt ret <8 x i16> %shl } ;; Before (with -mattr=+avx): vmovd %xmm1, %eax movzwl %ax, %eax vmovd %eax, %xmm1 vpsllw %xmm1, %xmm0, %xmm0 retq Now: vpxor %xmm2, %xmm2, %xmm2 vpblendw $1, %xmm1, %xmm2, %xmm1 vpsllw %xmm1, %xmm0, %xmm0 retq llvm-svn: 223660
* X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.hElena Demikhovsky2014-12-082-133/+48
| | | | | | | | X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of this long switch to the new intrinsics table in X86IntrinsicsInfo.h. No functional changes, just code and compile time optimization. llvm-svn: 223641
* R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOPMarek Olsak2014-12-071-8/+46
| | | | | | This is only a workaround. llvm-svn: 223615
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-076-20/+85
| | | | llvm-svn: 223614
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-073-1/+48
| | | | | | | | | There are 3 changes: - Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI - Lower RSQ_CLAMP for VI - Don't generate MIN/MAX_LEGACY on VI llvm-svn: 223604
* R600/SI: Add VI instructionsMarek Olsak2014-12-0712-651/+1439
| | | | llvm-svn: 223603
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