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* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-288-2/+609
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-281-1/+1
| | | | | | | | it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> llvm-svn: 162741
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-283-18/+10
| | | | llvm-svn: 162740
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-283-31/+18
| | | | llvm-svn: 162738
* Fix PR12312Michael Liao2012-08-281-10/+112
| | | | | | | | | | - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-286-169/+43
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Fix mips' long branch pass.Akira Hatanaka2012-08-281-105/+128
| | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. llvm-svn: 162731
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Allow remat of LI on PPC.Hal Finkel2012-08-282-1/+3
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-283-8/+34
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+9
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen2012-08-281-3/+3
| | | | llvm-svn: 162714
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-276-43/+169
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-271-2/+3
| | | | | | <rdar://problem/12183003> llvm-svn: 162703
* Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper2012-08-271-56/+0
| | | | | | SelectionDAGBuilder. llvm-svn: 162661
* Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper2012-08-271-13/+9
| | | | | | unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. llvm-svn: 162658
* Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper2012-08-271-4/+4
| | | | | | removing the need for an explicit 'neverHasSideEffects = 1' llvm-svn: 162656
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-272-48/+62
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-248-25/+22
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen2012-08-241-1/+2
| | | | llvm-svn: 162622
* Missed tLEApcrelJT.Jakob Stoklund Olesen2012-08-241-0/+1
| | | | | | | ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. llvm-svn: 162615
* Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen2012-08-242-0/+4
| | | | | | | | | | It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. llvm-svn: 162603
* Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen2012-08-241-34/+16
| | | | | | | | | The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. llvm-svn: 162593
* Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen2012-08-241-2/+5
| | | | | | | There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. llvm-svn: 162592
* Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka2012-08-241-1/+3
| | | | llvm-svn: 162589
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-241-2/+3
| | | | | | second operand is MipsISD::GPRel. llvm-svn: 162584
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-243-7/+40
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* Fix load/store SDNode flags.Jakob Stoklund Olesen2012-08-241-2/+2
| | | | llvm-svn: 162558
* Add missing SDNPSideEffect flags.Jakob Stoklund Olesen2012-08-243-11/+17
| | | | llvm-svn: 162557
* Remove more mayLoad workarounds.Jakob Stoklund Olesen2012-08-241-7/+7
| | | | llvm-svn: 162556
* Custom lower FMA intrinsics to target specific nodes and remove the patterns.Craig Topper2012-08-243-132/+73
| | | | llvm-svn: 162534
* Fix undefined behavior (negation of INT_MIN) in ARM backend.Richard Smith2012-08-242-2/+2
| | | | llvm-svn: 162520
* Remove some spurious mayLoad = 0 flags.Jakob Stoklund Olesen2012-08-241-14/+8
| | | | | | | They were inserted to silence TableGen's warning about redundant properties. That warning is now gone. llvm-svn: 162517
* Add missing SDNP properties on the flushw node.Jakob Stoklund Olesen2012-08-241-1/+1
| | | | llvm-svn: 162515
* X86MemBarrier has unmodeled side effects.Jakob Stoklund Olesen2012-08-241-1/+1
| | | | llvm-svn: 162514
* Preserve operand flags in convertToThreeAddress() by copying operands.Jakob Stoklund Olesen2012-08-231-67/+52
| | | | | | No test case, this is a generalization of r160260. llvm-svn: 162485
* Favor FMA3 over FMA4 if both are enabled.Craig Topper2012-08-231-1/+2
| | | | llvm-svn: 162454
* Use a switch statement instead of a bunch of if-else checks and pull out the ↵Craig Topper2012-08-231-8/+10
| | | | | | common function call. llvm-svn: 162428
* Remove unused private field to silence build warning.Craig Topper2012-08-233-7/+4
| | | | llvm-svn: 162426
* Make function loadImmediate a member of MipsSEInstrInfo and change it to returnAkira Hatanaka2012-08-235-65/+54
| | | | | | | | | | the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. llvm-svn: 162417
* Add a member of type Mips16InstrInfo/MipsSEInstrInfo to classAkira Hatanaka2012-08-226-13/+15
| | | | | | | | Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. llvm-svn: 162413
* [ms-inline asm] Avoid a false positive assertionChad Rosier2012-08-221-1/+3
| | | | | | | | | | | Assertion failed: (Start.isValid() == End.isValid() && "Start and end should either both be valid or both be invalid!") when parsing inline asm. SMLoc assumes that the first char * in the source is invalid. However, when parsing an inline asm the mnemonic is at this location. I don't want to change SMLoc, so use a trivial workaround. llvm-svn: 162381
* Reduce duplicated hash map lookups.Benjamin Kramer2012-08-221-3/+2
| | | | llvm-svn: 162362
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-227-11/+7
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Don't cache the MBB in the class. Its only used by one function. Change a ↵Craig Topper2012-08-221-5/+3
| | | | | | for loop over operands to use unsigned instead of int. llvm-svn: 162344
* Mark a function as static since it doesn't use anything in the class.Craig Topper2012-08-221-1/+1
| | | | llvm-svn: 162342
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-226-7/+22
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Add option disable-mips-delay-filler. Turn on mips' delay slot filler byAkira Hatanaka2012-08-221-4/+5
| | | | | | | | default. Patch by Carl Norum. llvm-svn: 162339
* For mips64 switch statements in subroutines could generate Jack Carter2012-08-221-1/+1
| | | | | | | | | | | | | within the codegen EK_GPRel64BlockAddress. This was not supported for direct object output and resulted in an assertion. This change adds support for EK_GPRel64BlockAddress for direct object. One fallout from this is to turn on rela relocations for mips64 to match gas. llvm-svn: 162334
* Add a few functions to TargetLibraryInfo as part of PR13574.Chad Rosier2012-08-211-0/+36
| | | | | | Patch by Weiming Zhao <weimingz@codeaurora.org>. llvm-svn: 162329
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