summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper2012-09-162-2/+2
| | | | llvm-svn: 164001
* The PMOVZXWD family of functions had patterns extends narrow vector types to ↵Nadav Rotem2012-09-161-0/+24
| | | | | | | | | | | wide vector types. It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast, and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics. rdar://11897677 llvm-svn: 163995
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-154-9/+9
| | | | llvm-svn: 163974
* Remove unused private fields to silence -Wunused-private-field.Craig Topper2012-09-151-9/+6
| | | | llvm-svn: 163973
* X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math.Benjamin Kramer2012-09-151-0/+2
| | | | | | This was only an issue if sse is disabled. llvm-svn: 163967
* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-156-146/+52
| | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. llvm-svn: 163960
* Handled unaligned load/stores properly in Mips16 Akira Hatanaka2012-09-151-2/+7
| | | | | | Patch by Reed Kotler. llvm-svn: 163956
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
* DAG post-process for Hexagon MI schedulerSergei Larin2012-09-142-0/+34
| | | | | | | | This patch introduces a possibility for Hexagon MI scheduler to perform some target specific post- processing on the scheduling DAG prior to scheduling. llvm-svn: 163903
* Fix Doxygen issues:Dmitri Gribenko2012-09-145-20/+20
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* Remove redundant private field.Benjamin Kramer2012-09-142-3/+2
| | | | | | clang warned about this being unused in Release builds. llvm-svn: 163899
* mips16 fixes.Akira Hatanaka2012-09-142-2/+16
| | | | | | | | | 1. Add MoveR3216 2. Correct spelling for Move32R16 Patch by Reed Kotler. llvm-svn: 163869
* Fix commentMichael Liao2012-09-131-1/+1
| | | | llvm-svn: 163835
* Add wider vector/integer support for PR12312Michael Liao2012-09-132-100/+103
| | | | | | | | - Enhance the fix to PR12312 to support wider integer, such as 256-bit integer. If more than 1 fully evaluated vectors are found, POR them first followed by the final PTEST. llvm-svn: 163832
* Fix the TCRETURNmi64 bug differently.Jakob Stoklund Olesen2012-09-131-2/+21
| | | | | | | | | | Add a PatFrag to match X86tcret using 6 fixed registers or less. This avoids folding loads into TCRETURNmi64 using 7 or more volatile registers. <rdar://problem/12282281> llvm-svn: 163819
* mips16: When copying operands in a conditional branch instruction, allow forAkira Hatanaka2012-09-131-3/+9
| | | | | | | | immediate operands to be copied. Patch by Reed Kotler. llvm-svn: 163811
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-133-39/+1
| | | | | | The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-139-30/+41
| | | | llvm-svn: 163803
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-133-1/+39
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Misc.Akira Hatanaka2012-09-121-3/+6
| | | | | | | | | 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
* Fix PR11985Michael Liao2012-09-127-25/+36
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-1/+1
| | | | llvm-svn: 163721
* Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky2012-09-121-2/+1
| | | | | | was fixed in r163713. llvm-svn: 163715
* This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky2012-09-124-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! llvm-svn: 163713
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
| | | | llvm-svn: 163710
* Indentation fixes. No functional change.Craig Topper2012-09-121-8/+8
| | | | llvm-svn: 163682
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Release build: guard dump functions withManman Ren2012-09-112-2/+2
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+4
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Make a bunch of lowering helper functions static instead of member ↵Craig Topper2012-09-112-82/+56
| | | | | | functions. No functional change. llvm-svn: 163596
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-112-510/+18
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-107-14/+14
| | | | llvm-svn: 163561
* Revert r163556. Missed updates to tablegen files.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163557
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163556
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-103-3/+3
| | | | llvm-svn: 163547
* [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier2012-09-102-4/+6
| | | | | | and update the printOperand() function accordingly. llvm-svn: 163544
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-103-7/+15
| | | | | | - Fix an remaining issue of PR11674 as well llvm-svn: 163528
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Add boolean simplification support from CMOVMichael Liao2012-09-101-12/+42
| | | | | | | | - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. llvm-svn: 163516
* The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky2012-09-101-4/+15
| | | | | | | | undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. llvm-svn: 163506
* Make helper function static.Benjamin Kramer2012-09-101-2/+1
| | | | llvm-svn: 163504
* Add missing space before {. No functionality change.Nick Lewycky2012-09-091-1/+1
| | | | llvm-svn: 163484
OpenPOWER on IntegriCloud