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* Add missing builtins to the PPC back end for ABI compliance (vol. 1)Nemanja Ivanovic2015-06-261-6/+18
| | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10638 This is the back end portion of patch http://reviews.llvm.org/D10637 It just adds the code gen and intrinsic functions necessary to support that patch to the back end. llvm-svn: 240820
* Revert "Revert r240762 "[X86] Cleanup ↵David Majnemer2015-06-261-36/+28
| | | | | | | | | | | X86WindowsTargetObjectFile::getSectionForConstant"" This reverts commit r240793 while fixing how we handle array constant pool entries. This fixes PR23966. llvm-svn: 240811
* Add op_values() to iterate over the SDValue operands of an SDNode.Pete Cooper2015-06-261-2/+1
| | | | | | | | | | SDNode already had ops() which would iterate over the operands and return SDUse*. This version instead gets the SDValue's out of the SDUse's so that we can use foreach in more places. Reviewed by David Blaikie. llvm-svn: 240805
* [ARM] Cortex-R5 is not VFPOnlySPJaved Absar2015-06-261-1/+1
| | | | | | | | | | | | | This patch fixes the error in ARM.td which stated that Cortex-R5 floating point unit can do only single precision, when it can do double as well. Reviewers: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10769 llvm-svn: 240799
* [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.Douglas Katzman2015-06-261-1/+7
| | | | | | | | Patch by Matthew Barney. Thanks! Differential Revision: http://reviews.llvm.org/D9514 llvm-svn: 240795
* Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant"Hans Wennborg2015-06-261-25/+37
| | | | | | It seems to have caused PR23966: "UNREACHABLE executed at ..\lib\Target\X86\X86TargetObjectFile.cpp:148" llvm-svn: 240793
* Rename getObjectFile to getObject for consistency.Rafael Espindola2015-06-262-2/+2
| | | | llvm-svn: 240785
* [mips] [IAS] Add partial support for the ULW pseudo-instruction.Toma Tabacu2015-06-262-0/+82
| | | | | | | | | | | | | | | | Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
* [ARM] Cortex-R4F is not VFPOnlySPJaved Absar2015-06-261-1/+1
| | | | | | | | | | | | | Cortex-R4F TRM states that fpu supports both single and double precision. This patch corrects the information in ARM.td file and corresponding test. Reviewers: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10763 llvm-svn: 240776
* Optimize the creation of mapping symbols.Rafael Espindola2015-06-262-19/+2
| | | | | | No need to create two symbols just to assign one to the other. llvm-svn: 240773
* [X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstantDavid Majnemer2015-06-261-37/+25
| | | | | | No functionality changed, just keeping things clean. llvm-svn: 240762
* [ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.Hao Liu2015-06-265-0/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch also adds a function to calculate the cost of interleaved memory accesses. E.g. Lower an interleaved load: %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4 %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> into: %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4) %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0 %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1 E.g. Lower an interleaved store: %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4 into: %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3> %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7> %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4) Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240755
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This ↵Hao Liu2015-06-265-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | patch also adds a function to calculate the cost of interleaved memory accesses. E.g. Lower an interleaved load: %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> into: %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr) %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0 %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1 E.g. Lower an interleaved store: %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr into: %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3> %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7> %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr) Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240754
* Revert "X86: Reject register operands with obvious type mismatches."Matthias Braun2015-06-261-13/+0
| | | | | | | | Revert until http://llvm.org/PR23955 is investigated. This reverts commit r239309. llvm-svn: 240746
* PPCISelLowering.cpp: Appease PR23956. [-Wdocumentation]NAKAMURA Takumi2015-06-251-6/+6
| | | | llvm-svn: 240727
* Add an ELFSymbolRef type.Rafael Espindola2015-06-251-2/+2
| | | | | | | This allows user code to say Sym.getSize() instead of having to manually fetch the object. llvm-svn: 240708
* Use foreach loop over constant operands. NFC.Pete Cooper2015-06-251-2/+1
| | | | | | | A number of places had explicit loops over Constant::operands(). Just use foreach loops where possible. llvm-svn: 240694
* [PPC] Implement vmrgew and vmrgow instructionsKit Barton2015-06-253-2/+154
| | | | | | | | | This patch adds support for the vector merge even word and vector merge odd word instructions introduced in POWER8. Phabricator review: http://reviews.llvm.org/D10704 llvm-svn: 240650
* [PPC] Replace debug value skipping with getLastNonDebugInstr.Benjamin Kramer2015-06-251-16/+7
| | | | | | No functionality change intended. llvm-svn: 240641
* Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstrBenjamin Kramer2015-06-254-48/+20
| | | | | | No functional change intended. llvm-svn: 240639
* [mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.Toma Tabacu2015-06-253-28/+25
| | | | | | | | | | | | | | | | | | | | Summary: Simplify emitDirectiveModuleFP() by having it just print the current information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10642 llvm-svn: 240637
* [SystemZ] Only attempt RxSBG optimization for integer typesUlrich Weigand2015-06-251-2/+7
| | | | | | | | | | | | As pointed out by Justin Bogner (see r240520), SystemZDAGToDAGISel::Select currently attempts to convert boolean operations into RxSBG even on some non-integer types (in particular, vector types). This would not work in any case, and it happened to trigger undefined behaviour in allOnes. This patch verifies that we have a (<= 64-bit) integer type before attempting to perform this optimization. llvm-svn: 240634
* [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.Toma Tabacu2015-06-254-22/+26
| | | | | | | | | | | | | | | | | | | Summary: We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10641 llvm-svn: 240630
* [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.Toma Tabacu2015-06-251-2/+5
| | | | | | | | | | | | | | | | | | | Summary: In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser. This means that we can only parse one level of inner parentheses. In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions (except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression(). Reviewers: dsanders, rafael Reviewed By: dsanders, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9742 llvm-svn: 240625
* [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.Ahmed Bougacha2015-06-251-3/+5
| | | | | | | | | | We don't always have FMA, for example when using 'clang -mavx512f' without an explicit CPU. Also check for an explicit +avx512f instead of CPUs in a couple related tests. llvm-svn: 240616
* Enable StackMap Serialization for COFFSwaroop Sridhar2015-06-251-0/+2
| | | | | | | | | | | | | | | | | | Summary This change turns on the emission of __LLVM_Stackmaps section when generating COFF binaries. Test Plan Added a scenario to the test case: test\CodeGen\X86\statepoint-stackmap-format.ll. Code Review: http://reviews.llvm.org/D10680 llvm-svn: 240613
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* Add NVPTXPeephole pass to reduce unnecessary address castJingyue Wu2015-06-246-16/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch first change the register that holds local address for stack frame to %SPL. Then the new NVPTXPeephole pass will try to scan the following pattern %vreg0<def> = LEA_ADDRi64 <fi#0>, 4 %vreg1<def> = cvta_to_local %vreg0 and transform it into %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4 Patched by Xuetian Weng Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: eliben, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10549 llvm-svn: 240587
* ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually ↵Matthias Braun2015-06-241-107/+112
| | | | | | | | | | test for it This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 llvm-svn: 240582
* [mips][microMIPS] Implement BREAK, EHB and EI instructionsZoran Jovanovic2015-06-244-2/+63
| | | | | | http://reviews.llvm.org/D10090 llvm-svn: 240531
* Change how symbol sizes are handled in lib/Object.Rafael Espindola2015-06-241-1/+1
| | | | | | | | | | | | | | COFF and MachO only define symbol sizes for common symbols. Reflect that in the class hierarchy by having a method for common symbols only in the base and a general one in ELF. This avoids the need of using a magic value for the size, which had a few problems * Most callers didn't check for it. * The ones that did could not tell the magic value from a file actually having that value. llvm-svn: 240529
* Hexagon: Paper over the undefined behaviour introduced by r238692Justin Bogner2015-06-242-1/+3
| | | | | | | | | | | | | | | | This stops shifting a 32-bit value by such absurd amounts as 96 and 120. We do this by dropping a call to the function that was doing this entirely, which rather surprisingly doesn't break *any* tests. I've also added an assert in the misbehaving function to prove that it's no longer being called with completely invalid arguments. This change looks pretty bogus and we should probably be reverting r238692 instead, but this is hard to do with the number of follow ups that have happened since. It can't be any worse than the undefined behaviour that was happening before though. llvm-svn: 240526
* Hexagon: Avoid left shifting negative values (it's UB)Justin Bogner2015-06-241-1/+1
| | | | | | Found by ubsan. llvm-svn: 240521
* SystemZ: Rephrase this allOnes calculation to avoid UBJustin Bogner2015-06-241-1/+3
| | | | | | | | | | | | | This allOnes function hits undefined behaviour if Count is greater than 64, but we can avoid that and simplify the calculation by just saturating if such a value is passed in. This comes up under ubsan becauseRxSBGOperands is sometimes created with values that are 128 bits wide. Somebody more familiar with this code should probably look into whether that's expected, as a 64 bit mask may or may not be appropriate for such types. llvm-svn: 240520
* [X86] Don't generate vbroadcasti128 for v4i64 splats from memory.Ahmed Bougacha2015-06-241-4/+5
| | | | | | | | | | | | | | | | | | | | | We used to erroneously match: (v4i64 shuffle (v2i64 load), <0,0,0,0>) Whereas vbroadcasti128 is more like: (v4i64 shuffle (v2i64 load), <0,1,0,1>) This problem doesn't exist for vbroadcastf128, which kept matching the intrinsic after r231182. We should perhaps re-introduce the intrinsic here as well, but that's a separate issue still being discussed. While there, add some proper vbroadcastf128 tests. We don't currently match those, like for loading vbroadcastsd/ss on AVX (the reg-reg broadcasts where added in AVX2). Fixes PR23886. llvm-svn: 240488
* [ARM] ARMLoadStoreOpt::UpdateBaseRegUses should stop on defJohn Brawn2015-06-231-1/+1
| | | | | | | | | | | | When UpdateBaseRegUses sees an instruction that defines the base register it must stop, as the base register value it is updating is no longer live. Ideally we would already have seen the register be killed (which is already checked for), but the kill flags may be inaccurate and we have to account for this. Differential Revision: http://reviews.llvm.org/D10566 llvm-svn: 240424
* SystemZ: Avoid left shifting negative values (it's UB)Justin Bogner2015-06-231-4/+4
| | | | | | Found by ubsan. llvm-svn: 240420
* Make helper functions static. NFC.Benjamin Kramer2015-06-231-3/+4
| | | | llvm-svn: 240416
* [mips] [IAS] Add partial support for the ULHU pseudo-instruction.Toma Tabacu2015-06-232-0/+114
| | | | | | | | | | | | | | | | Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
* [mips] [IAS] Add support for generating DADDu to createAddu(). NFC.Toma Tabacu2015-06-231-7/+7
| | | | | | | | | | | | | | Summary: This isn't used right now, but it will be in some upcoming changes. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10568 llvm-svn: 240407
* Simplify the Mangler interface now that DataLayout is mandatory.Rafael Espindola2015-06-233-3/+3
| | | | | | | We only need to pass in a DataLayout when mangling a raw string, not when constructing the mangler. llvm-svn: 240405
* [mips64] Emit correct addend for some PC-relative relocationsPetar Jovanovic2015-06-232-12/+9
| | | | | | | | | | | So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
* [Hexagon] Use MF reference from parent class in HexagonPacketizerListKrzysztof Parzyszek2015-06-231-10/+7
| | | | llvm-svn: 240403
* [mips] [IAS] Move some function definitions to MipsTargetStreamer.cpp. NFC.Toma Tabacu2015-06-232-8/+13
| | | | | | | | | | | | | | Summary: For the sake of consistency and to make some upcoming changes a little less noisy. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10639 llvm-svn: 240398
* Use MCSymbols for FastISel.Rafael Espindola2015-06-236-24/+38
| | | | | | | | | | | The summary is that it moves the mangling earlier and replaces a few calls to .addExternalSymbol with addSym. I originally wanted to replace all the uses of addExternalSymbol with addSym, but noticed it was a lot of work and doesn't need to be done all at once. llvm-svn: 240395
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-23278-336/+336
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* AVX-512: Added all forms of VPABS instructionElena Demikhovsky2015-06-235-71/+105
| | | | | | Added all intrinsics, tests for encoding, tests for intrinsics. llvm-svn: 240386
* [mips] Fix some UB by shifting before sign-extendingJustin Bogner2015-06-231-1/+1
| | | | | | | | Avoid shifting a negative value by sign-extending after the shift. Fixes a couple of tests that were failing under ubsan. llvm-svn: 240381
* AMDGPU: Use getAsInteger instead of atoiMatt Arsenault2015-06-231-3/+5
| | | | llvm-svn: 240365
* [x86] generalize reassociation optimization in machine combiner to 2 ↵Sanjay Patel2015-06-231-77/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instructions Currently ( D10321, http://reviews.llvm.org/rL239486 ), we can use the machine combiner pass to reassociate the following sequence to reduce the critical path: A = ? op ? B = A op X C = B op Y --> A = ? op ? B = X op Y C = A op B 'op' is currently limited to x86 AVX scalar FP adds (with fast-math on), but in theory, it could be any associative math/logic op (see TODO in code comment). This patch generalizes the pattern match to ignore the instruction that defines 'A'. So instead of a sequence of 3 adds, we now only need to find 2 dependent adds and decide if it's worth reassociating them. This generalization has a compile-time cost because we can now match more instruction sequences and we rely more heavily on the machine combiner to discard sequences where reassociation doesn't improve the critical path. For example, in the new test case: A = M div N B = A add X C = B add Y We'll match 2 reassociation patterns, but this transform doesn't reduce the critical path: A = M div N B = A add Y C = B add X We need the combiner to reject that pattern but select this: A = M div N B = X add Y C = B add A Differential Revision: http://reviews.llvm.org/D10460 llvm-svn: 240361
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