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* Add a SPR register class to the ARM target.Jakob Stoklund Olesen2009-12-222-1/+14
| | | | | | Certain Thumb instructions require only SP (e.g. tSTRspi). llvm-svn: 91944
* Removed the "inline" keyword from the disassembler decoder,Sean Callanan2009-12-221-30/+30
| | | | | | because the Visual C++ build does not build .c files as C99 llvm-svn: 91935
* Fixes to the X86 disassembler:Sean Callanan2009-12-222-5/+17
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Use proper move instructions. Make the verifier happy.Jakob Stoklund Olesen2009-12-221-1/+1
| | | | llvm-svn: 91914
* Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng2009-12-226-42/+18
| | | | | | partial update instructions unless optimizing for size. llvm-svn: 91910
* Include based on the current path, since we already -I the X86 target's ↵Douglas Gregor2009-12-221-1/+1
| | | | | | path. Fixes CMake build llvm-svn: 91908
* While converting one of the operands to a memory operand, we need to check ↵Sanjiv Gupta2009-12-223-10/+45
| | | | | | if it is Legal and does not result into a cyclic dep. llvm-svn: 91904
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-226-8/+11
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* Changed REG_* to MODRM_REG_* to avoid conflictsSean Callanan2009-12-222-17/+21
| | | | | | with symbols in AuroraUX's global namespace. llvm-svn: 91879
* Fix some may-be-uninitialized var warnings.Daniel Dunbar2009-12-221-3/+3
| | | | llvm-svn: 91878
* Fixed library dependencies between the X86 disassembler andSean Callanan2009-12-223-18/+5
| | | | | | X86 codegen that were causing circular symbol dependencies. llvm-svn: 91871
* print pcrel immediates as signed values instead of unsigned so that weChris Lattner2009-12-221-3/+5
| | | | | | | | | | | | | | get things like this out of the disassembler: 0x100000ecb: callq -96 instead of: 0x100000ecb: callq 4294967200 rdar://7491123 llvm-svn: 91864
* Mark FPW as allocable when frame address is taken.Anton Korobeynikov2009-12-211-5/+43
| | | | llvm-svn: 91841
* Delete the instruction just before the function terminates for consistency sake.Evan Cheng2009-12-211-2/+3
| | | | llvm-svn: 91836
* Fix setting and default setting of code model for jit. Do thisEric Christopher2009-12-213-16/+25
| | | | | | | | | | by allowing backends to override routines that will default the JIT and Static code generation to an appropriate code model for the architecture. Should fix PR 5773. llvm-svn: 91824
* A couple minor README updates.Eli Friedman2009-12-211-14/+5
| | | | llvm-svn: 91823
* Remove unused variable (noticed by clang++).Daniel Dunbar2009-12-191-1/+0
| | | | llvm-svn: 91780
* #if 0 out X86 disassembler for now, it is breaking the build in multiple places.Daniel Dunbar2009-12-192-0/+13
| | | | llvm-svn: 91778
* Emit direction operand in binary insns that stores in memory.Sanjiv Gupta2009-12-191-1/+1
| | | | llvm-svn: 91777
* rename dprintf to dbgpritnf, in order to fix build with glibc (which already ↵Nuno Lopes2009-12-191-29/+29
| | | | | | defines dprintf in stdio.h llvm-svn: 91775
* 1. In indirect load/store insns , the name of fsr should be emitted as INDF.Sanjiv Gupta2009-12-191-5/+13
| | | | | | 2. include standard asmbly headers in generated asmbly. llvm-svn: 91768
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-192-14/+14
| | | | llvm-svn: 91764
* Use memset instead of bzero, its more portable.Daniel Dunbar2009-12-191-2/+2
| | | | llvm-svn: 91754
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-199-5/+2823
| | | | | | | | | | | | | | | | | | | | incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
* Bump alignment requirements for windows targets to achieve compartibility ↵Anton Korobeynikov2009-12-191-0/+3
| | | | | | | | with vcpp. Based on patch by Michael Beck! llvm-svn: 91745
* Changes from review:Bill Wendling2009-12-181-0/+6
| | | | | | | | | | | - Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. llvm-svn: 91727
* Fix libstdc++ build on ARM linux and part of PR5770.Rafael Espindola2009-12-181-0/+3
| | | | | | | | | | | | | | MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done. Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts. For a patch that make us detect problems like this earlier, take a look at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html With that patch we assert as soon and the new instruction is added to the garbage set. llvm-svn: 91691
* Fix wrong frame pointer save offset in the 64-bit PowerPC SVR4 ABI.Tilmann Scheller2009-12-181-1/+1
| | | | | | Patch contributed by Ken Werner of IBM! llvm-svn: 91681
* Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI.Tilmann Scheller2009-12-184-3/+141
| | | | | | Patch contributed by Ken Werner of IBM! llvm-svn: 91680
* On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng2009-12-186-17/+82
| | | | | | | | | | | | | | | | | | | be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
* Fix typo.Eric Christopher2009-12-181-1/+1
| | | | llvm-svn: 91657
* Re-apply 91623 now that I actually know what I was trying to do.Evan Cheng2009-12-181-25/+1
| | | | llvm-svn: 91655
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-2/+2
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* Pass the error string directly to llvm_unreachable instead of the residualJohn McCall2009-12-181-1/+1
| | | | | | | | | (0 && "error"). Rough consensus seems to be that g++ *should* be diagnosing this because the pointer makes it not an ICE in c++03. Everyone agrees that the current standard is silly and null-pointer-ness should not be based on ICE-ness. Excellent fight scene in Act II, denouement weak, two stars. llvm-svn: 91644
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-189-423/+1236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Revert r91623 to unbreak the buildbots.Jeffrey Yasskin2009-12-171-1/+4
| | | | llvm-svn: 91632
* Remove an unused option.Evan Cheng2009-12-171-4/+1
| | | | llvm-svn: 91623
* finish cleaning up StructLayoutMap.Chris Lattner2009-12-171-21/+17
| | | | llvm-svn: 91612
* In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead ofKen Dyck2009-12-171-1/+1
| | | | | | | incrementing the simple value type of the 16-bit type, which would give the wrong type if an intemediate MVT (such as i24) were introduced. llvm-svn: 91602
* Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.Johnny Chen2009-12-161-1/+1
| | | | llvm-svn: 91571
* Silence a clang warning about the deprecated (but perfectly reasonable inJohn McCall2009-12-161-2/+2
| | | | | | context) increment-of-bool idiom. llvm-svn: 91564
* Mark STREX* as earlyclobber for the success result register.Jim Grosbach2009-12-162-2/+2
| | | | llvm-svn: 91555
* Add encoding bits for some Thumb instructions. Plus explicitly set the top twoJohnny Chen2009-12-163-10/+18
| | | | | | bytes of Inst to 0x0000 for the benefit of the Thumb decoder. llvm-svn: 91496
* Re-enable 91381 with fixes.Evan Cheng2009-12-163-12/+40
| | | | llvm-svn: 91489
* Every anonymous namespace is different. Caught by clang++.John McCall2009-12-161-4/+0
| | | | llvm-svn: 91481
* Change indirect-globals to use a dedicated allocIndirectGV. This lets usJeffrey Yasskin2009-12-154-21/+15
| | | | | | | | | remove start/finishGVStub and the BufferState helper class from the MachineCodeEmitter interface. It has the side-effect of not setting the indirect global writable and then executable on ARM, but that shouldn't be necessary. llvm-svn: 91464
* Added encoding bits for the Thumb ISA. Initial checkin.Johnny Chen2009-12-153-348/+1219
| | | | llvm-svn: 91434
* Fix an encoding bug.Evan Cheng2009-12-151-1/+1
| | | | llvm-svn: 91417
* For fastcc on x86, let ECX be used as a return register after EAX and EDXKenneth Uildriks2009-12-151-1/+8
| | | | llvm-svn: 91410
* Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.Evan Cheng2009-12-151-1/+3
| | | | llvm-svn: 91405
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