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* [ARM] Fix handling of thumb1 out-of-range frame offsetsJohn Brawn2015-03-206-11/+12
| | | | | | | | | | | | | | | | LocalStackSlotPass assumes that isFrameOffsetLegal doesn't change its answer when the base register changes. Unfortunately this isn't true in thumb1, where SP-based loads allow a larger offset than non-SP-based loads, and this causes the base register reuse code to generate instructions that are unencodable, causing an assertion failure. Solve this by adding a BaseReg parameter to isFrameOffsetLegal, which ARMBaseRegisterInfo can then make use of to give the correct answer. Differential Revision: http://reviews.llvm.org/D8419 llvm-svn: 232825
* Stripped trailing whitespace. NFC.Simon Pilgrim2015-03-201-15/+15
| | | | llvm-svn: 232822
* R600/SI: Refactor VOP2 instruction defsTom Stellard2015-03-201-6/+13
| | | | llvm-svn: 232817
* R600/SI: Refactor VOP1 instruction defsTom Stellard2015-03-201-7/+12
| | | | llvm-svn: 232816
* Reduce indentation after return. NFC.Rafael Espindola2015-03-201-138/+125
| | | | llvm-svn: 232814
* Use early returns. NFC.Rafael Espindola2015-03-201-104/+50
| | | | llvm-svn: 232813
* Fold a llvm_unreachable into an assert. NFC.Rafael Espindola2015-03-201-3/+3
| | | | llvm-svn: 232811
* clang-format a function. NFC.Rafael Espindola2015-03-201-12/+32
| | | | llvm-svn: 232810
* [Tablegen] Attempt to add support for patterns containing nodes with ↵Craig Topper2015-03-201-6/+6
| | | | | | | | | | multiple results. This is needed for AVX512 masked scatter/gather support. The R600 change is necessary to remove a hack that was working around the lack of multiple results. llvm-svn: 232798
* [bpf] fix buildAlexei Starovoitov2015-03-201-2/+1
| | | | | | fix BPF backend build broken by r232699 llvm-svn: 232795
* move insert, extract, concat helper functions closer to related helper ↵Sanjay Patel2015-03-191-156/+156
| | | | | | functions; NFCI llvm-svn: 232781
* Add an MCSubtargetInfo variable to the TargetMachine.Eric Christopher2015-03-191-1/+3
| | | | | | | | | This enables us to remove calls to the subtarget from the TargetMachine and with a small hack for backends that require global subtarget information for module level code generation, e.g. mips abi flags, as mentioned in a fixme in the code. llvm-svn: 232776
* Add a TargetMachine local MCRegisterInfo and MCInstrInfo so thatEric Christopher2015-03-191-2/+5
| | | | | | | they can be used without a subtarget in constructing subtarget independent passes. llvm-svn: 232775
* [X86, AVX] use blends instead of insert128 with index 0Sanjay Patel2015-03-191-1/+44
| | | | | | | | | | | | | | | Another case of x86-specific shuffle strength reduction: avoid generating insert*128 instructions with index 0 because they are slower than their non-lane-changing blend equivalents. Shuffle lowering already catches most of these cases, but the zero vector case and some other paths such as in the modified test in vector-shuffle-256-v32.ll were getting through. Differential Revision: http://reviews.llvm.org/D8366 llvm-svn: 232773
* Add support for __nvvm_reflect changes in libdevice in CUDA-7.0Artem Belevich2015-03-191-5/+32
| | | | | | | | | | | | | | | | | | Summary: CUDA 7.0's libdevice uses slightly different IR to call __nvvm_reflect and that triggers an assertion in nvvm_reflect optimization pass. This change allows nvvm_reflect pass to deal with both old and new ways to pass an argument to __nvvm_reflect. Test Plan: ninja check-all Reviewers: eliben, echristo Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8399 llvm-svn: 232732
* [Hexagon] Add support for vector instructionsKrzysztof Parzyszek2015-03-195-40/+1399
| | | | llvm-svn: 232728
* [Hexagon] ENDLOOP is a non-reversible conditional branchKrzysztof Parzyszek2015-03-191-0/+2
| | | | llvm-svn: 232725
* [sparc] Small fix to r232719 to make 2007-12-17-InvokeAsm.ll pass on the ↵Daniel Sanders2015-03-191-0/+1
| | | | | | buildbot. llvm-svn: 232720
* [sparc] Only support the 'm' inline assembly memory constraint. NFC.Daniel Sanders2015-03-191-6/+0
| | | | | | | | | | | | | | | | Summary: SPARC doesn't seem to support any additional constraints. Therefore remove the target hook. No functional change intended. Reviewers: venkatra Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8214 llvm-svn: 232719
* Split the object streamer callback in one per file format.Rafael Espindola2015-03-1917-115/+116
| | | | | | | | | | | | | There are two main advantages to doing this * Targets that only need to handle one of the formats specially don't have to worry about the others. For example, x86 now only registers a constructor for the COFF streamer. * Changes to the arguments passed to one format constructor will not impact the other formats. llvm-svn: 232699
* two or more, use a for.Rafael Espindola2015-03-188-457/+225
| | | | llvm-svn: 232688
* [X86][SSE] Avoid scalarization of v2i64 vector shifts (REAPPLIED)Simon Pilgrim2015-03-181-13/+24
| | | | | | | | Fixed broken tests. Differential Revision: http://reviews.llvm.org/D8416 llvm-svn: 232682
* [PowerPC] Correct typo in PPCInstrAltivec.tdBill Schmidt2015-03-181-1/+1
| | | | llvm-svn: 232681
* Revert "[X86][SSE] Avoid scalarization of v2i64 vector shifts" as itEric Christopher2015-03-181-24/+13
| | | | | | | | appears to have broken tests/bots. This reverts commit r232660. llvm-svn: 232670
* Revert "Add a TargetMachine local MCRegisterInfo and MCInstrInfo so that"Eric Christopher2015-03-181-4/+2
| | | | | | | | Committed too early. This reverts commit r232666. llvm-svn: 232667
* Add a TargetMachine local MCRegisterInfo and MCInstrInfo so thatEric Christopher2015-03-181-2/+4
| | | | | | | they can be used without a subtarget in constructing subtarget independent passes. llvm-svn: 232666
* Revert "Migrate the AArch64 TargetRegisterInfo to its TargetMachine"Eric Christopher2015-03-188-52/+48
| | | | | | | | | as we don't necessarily need to do this yet - though we could move the base class to the TargetMachine as it isn't subtarget dependent. This reverts commit r232103. llvm-svn: 232665
* [X86][SSE] Avoid scalarization of v2i64 vector shiftsSimon Pilgrim2015-03-181-13/+24
| | | | | | | | | | | | Currently v2i64 vectors shifts (non-equal shift amounts) are scalarized, costing 4 x extract, 2 x x86-shifts and 2 x insert instructions - and it gets even more awkward on 32-bit targets. This patch separately shifts the vector by both shift amounts and then shuffles the partial results back together, costing 2 x shuffles and 2 x sse-shifts instructions (+ 2 movs on pre-AVX hardware). Note - this patch only improves the SHL / LSHR logical shifts as only these are supported in SSE hardware. Differential Revision: http://reviews.llvm.org/D8416 llvm-svn: 232660
* Add a default implementation of createObjectStreamer.Rafael Espindola2015-03-183-42/+0
| | | | | | | This removes duplicated code from backends that don't need to do anything fancy. llvm-svn: 232658
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-182-22/+24
| | | | llvm-svn: 232657
* Revert "[Hexagon] Use pseudo-instructions for true/false predicate values"Krzysztof Parzyszek2015-03-181-6/+23
| | | | | | | | This reverts r232650. Missed a piece of code in the previous commit. llvm-svn: 232656
* Handle X86::reloc_riprel_4byte in 32 bits mode.Rafael Espindola2015-03-181-0/+1
| | | | | | | | We can get there with .code64. Fixes pr22349. llvm-svn: 232651
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-181-23/+6
| | | | llvm-svn: 232650
* [Hexagon] Intrinsics for circular and bit-reversed loads and storesKrzysztof Parzyszek2015-03-184-2/+398
| | | | llvm-svn: 232645
* [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranchKrzysztof Parzyszek2015-03-181-19/+28
| | | | llvm-svn: 232643
* [ARM] Align stack objects passed to memory intrinsicsJohn Brawn2015-03-182-0/+18
| | | | | | | | | | | | Memcpy, and other memory intrinsics, typically tries to use LDM/STM if the source and target addresses are 4-byte aligned. In CodeGenPrepare look for calls to memory intrinsics and, if the object is on the stack, 4-byte align it if it's large enough that we expect that memcpy would want to use LDM/STM to copy it. Differential Revision: http://reviews.llvm.org/D7908 llvm-svn: 232627
* [mips] Add itineraries for ext and ins instructions.Kai Nacke2015-03-182-2/+6
| | | | | | | | | | | Currently, there are no itineraries defined for ext and ins instructions. This patch adds these itineraries and uses them in the instruction definitions. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7209 llvm-svn: 232613
* [bpf] fix buildAlexei Starovoitov2015-03-181-1/+1
| | | | | | | | fix BPF backend build broken by r232429 Patch by Brenden Blanco llvm-svn: 232581
* Generate bit manipulation instructions on HexagonKrzysztof Parzyszek2015-03-181-0/+149
| | | | llvm-svn: 232577
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-172-1/+7
| | | | | | | | | | COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Differential Revision: http://reviews.llvm.org/D8394 llvm-svn: 232570
* Remove unneeded selection functions from HexagonISelDAGToDAGKrzysztof Parzyszek2015-03-171-189/+0
| | | | | | | - SelectSelect, and - SelectTruncate llvm-svn: 232569
* Fix bug while building FP16 constant vectors for AArch64Pirama Arumuga Nainar2015-03-171-2/+4
| | | | | | | | | | | | | | Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8369 llvm-svn: 232562
* Appease AArch64ISelLowering.cpp miscompiled by g++-4.7.2.NAKAMURA Takumi2015-03-171-0/+6
| | | | | | I will revert this when 4.7.3 is ready. llvm-svn: 232561
* Selection DAG preprocessing on HexagonKrzysztof Parzyszek2015-03-171-2/+52
| | | | | | Simplify: (or (select c x 0) z) -> (select c (or x z) z) (or (select c 0 y) z) -> (select c z (or y z)) llvm-svn: 232553
* Revert "COFF: Let globals with private linkage reside in their own section"David Majnemer2015-03-172-7/+1
| | | | | | This reverts commit r232539. This was committed accidently. llvm-svn: 232543
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-172-1/+7
| | | | | | | | | | | | | | | Summary: COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8374 llvm-svn: 232539
* Centralize the handling of unique ids for temporary labels.Rafael Espindola2015-03-172-6/+4
| | | | | | | | | | | | | | | | Before this patch code wanting to create temporary labels for a given entity (function, cu, exception range, etc) had to keep its own counter to have stable symbol names. createTempSymbol would still add a suffix to make sure a new symbol was always returned, but it kept a single counter. Because of that, if we were to use just createTempSymbol("cu_begin"), the label could change from cu_begin42 to cu_begin43 because some other code started using temporary labels. Simplify this by just keeping one counter per prefix and removing the various specialized counters. llvm-svn: 232535
* Add assertion to detect invalid registers in the PowerPC MC instruction ↵Samuel Antao2015-03-171-0/+3
| | | | | | | | lowering. We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst. llvm-svn: 232525
* [ARM] Fix offset calculation in ARMBaseRegisterInfo::needsFrameBaseRegRichard Barton2015-03-171-1/+0
| | | | | | | | | | | | | The input offset to needsFrameBaseReg is a negative value below the top of the stack frame, but when converting to a positive offset from the bottom of the stack frame this value was negated, causing the final offset to be too large by twice the input offset's magnitude. Fix that by not negating the offset. Patch by John Brawn Differential Revision: http://reviews.llvm.org/D8316 llvm-svn: 232513
* [systemz] Distinguish the 'Q', 'R', 'S', and 'T' inline assembly memory ↵Daniel Sanders2015-03-172-15/+38
| | | | | | | | | | | | | | | | | | | | constraints. Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: uweigand Reviewed By: uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8251 llvm-svn: 232495
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