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* Implement a bastardized ABI.Evan Cheng2012-04-272-3/+5
| | | | llvm-svn: 155686
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-272-16/+28
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd2012-04-261-0/+2
| | | | | | | | the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang llvm-svn: 155655
* Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover2012-04-261-56/+59
| | | | | | | On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
* Test commit.Tim Northover2012-04-261-2/+0
| | | | llvm-svn: 155626
* Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper2012-04-262-13/+9
| | | | | | corei7-avx, core-avx-i, and core-avx2 cpu names. llvm-svn: 155618
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-263-7/+16
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-252-4/+10
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-251-0/+1
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper2012-04-251-18/+20
| | | | | | ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. llvm-svn: 155537
* Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka2012-04-251-2/+2
| | | | llvm-svn: 155522
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-242-23/+42
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem2012-04-241-3/+30
| | | | | | | Remove the v2f64 patterns because it does not match any vbroadcast instruction. llvm-svn: 155461
* AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem2012-04-241-6/+0
| | | | | | | immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. llvm-svn: 155440
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem2012-04-241-1/+42
| | | | | | | | | using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). llvm-svn: 155437
* Remove dangling spaces. Fix some other formatting.Craig Topper2012-04-241-8/+10
| | | | llvm-svn: 155429
* Simplify code a bit and make it compile better. Remove unused parameters.Craig Topper2012-04-241-21/+10
| | | | llvm-svn: 155428
* Tidy up. 80 columns, whitespace, et. al.Jim Grosbach2012-04-234-59/+65
| | | | llvm-svn: 155399
* Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where ↵Nadav Rotem2012-04-231-0/+56
| | | | | | the integer type is i8 (commonly used in graphics). llvm-svn: 155397
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-2314-4/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* ARM: VSLI two-operand assmebly aliases are tblgen'erated.Jim Grosbach2012-04-231-19/+0
| | | | llvm-svn: 155393
* ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases.Jim Grosbach2012-04-231-58/+4
| | | | llvm-svn: 155392
* ARM: vqdmulh two-operand aliases are tblgen'erated now.Jim Grosbach2012-04-231-11/+0
| | | | llvm-svn: 155387
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-2335-11849/+2126
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
* Hexagon V5 (floating point) support.Sirish Pande2012-04-2320-1463/+3374
| | | | llvm-svn: 155367
* Support for Hexagon architectural feature, new value jump.Sirish Pande2012-04-238-5/+680
| | | | llvm-svn: 155366
* Support for Hexagon VLIW Packetizer.Sirish Pande2012-04-2319-685/+7822
| | | | llvm-svn: 155365
* Use MVT instead of EVT through all of LowerVECTOR_SHUFFLEtoBlend and not ↵Craig Topper2012-04-231-2/+2
| | | | | | just the switch. Saves a little bit of binary size. llvm-svn: 155339
* Make getZeroVector and getOnesVector more alike as far as how they detect ↵Craig Topper2012-04-231-13/+16
| | | | | | 128-bit versus 256-bit vectors. Be explicit about both sizes and use llvm_unreachable. Similar changes to getLegalSplat. llvm-svn: 155337
* Tidy up by removing some 'else' after 'return'Craig Topper2012-04-231-44/+60
| | | | llvm-svn: 155336
* Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if ↵Craig Topper2012-04-231-39/+34
| | | | | | shuffle operand has a different type than the the shuffle result since it can never happen. llvm-svn: 155333
* Add a couple llvm_unreachables.Craig Topper2012-04-231-0/+2
| | | | llvm-svn: 155332
* Remove some tab characers.Craig Topper2012-04-231-8/+8
| | | | llvm-svn: 155331
* Remove some 'else' after 'return'. No functional change.Craig Topper2012-04-231-3/+7
| | | | llvm-svn: 155330
* Make Extract128BitVector and Insert128BitVector take an unsigned instead of ↵Craig Topper2012-04-221-99/+68
| | | | | | an ConstantNode SDValue. getConstant was almost always called just before only to have the functions take it apart and build a new ConstantSDNode. llvm-svn: 155325
* Convert getNode(UNDEF) to getUNDEF.Craig Topper2012-04-221-6/+7
| | | | llvm-svn: 155321
* Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to ↵Craig Topper2012-04-221-8/+7
| | | | | | getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data(). llvm-svn: 155320
* Tidy up. 80 columns and argument alignment.Craig Topper2012-04-221-18/+17
| | | | llvm-svn: 155319
* Simplify code by converting multiple places that were manually concatenating ↵Craig Topper2012-04-221-20/+18
| | | | | | 128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs. llvm-svn: 155318
* ARM: Initialize the HasRAS bit.Benjamin Kramer2012-04-221-0/+1
| | | | | | Found by valgrind. llvm-svn: 155313
* ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky2012-04-223-14/+88
| | | | llvm-svn: 155309
* Remove some potential warnings about variables used uninitialized.Bill Wendling2012-04-221-1/+1
| | | | llvm-svn: 155307
* Make some fixed arrays const. Use array_lengthof in a couple places instead ↵Craig Topper2012-04-211-8/+8
| | | | | | of a hardcoded number. llvm-svn: 155294
* Tidy up. 80 columns and some other spacing issues.Craig Topper2012-04-211-7/+9
| | | | llvm-svn: 155291
* llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build ↵NAKAMURA Takumi2012-04-212-0/+3
| | | | | | | | on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
* HexagonISelLowering.cpp: Reorder #includes.NAKAMURA Takumi2012-04-211-1/+2
| | | | llvm-svn: 155286
* HexagonInstPrinter.cpp: Suppress -Wunused-variable warnings with -Asserts.NAKAMURA Takumi2012-04-211-6/+3
| | | | llvm-svn: 155281
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