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* [X86][SSE4A] Add support for combining from EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-031-0/+22
| | | | llvm-svn: 307048
* DAGCombine: Combine BUILD_VECTOR to TRUNCATEZvi Rackover2017-07-031-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a combine for creating a truncate to replace a build_vector composed of extracts with indices that form a stride-2^N series. Example: v8i32 V = ... v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6)) --> v4i32 truncate (bitcast V to v4i64) Related discussion in llvm-dev about canonicalizing shuffles to truncates in LLVM IR: http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html. Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena Reviewed By: delena Subscribers: guyblank, delena, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34077 llvm-svn: 307036
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-031-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307026
* [GlobalISel][X86] fix %ptr(p0) = G_CONSTANT selection.Igor Breger2017-07-031-1/+2
| | | | llvm-svn: 307019
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-033-3/+3
| | | | llvm-svn: 307004
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-022-0/+26
| | | | llvm-svn: 306995
* [X86][AVX512VPOPCNTDQ] Improve support for v16i8/v8i16/v16i16/ CTPOPSimon Pilgrim2017-07-021-0/+14
| | | | | | Zero extend to v16i32/v8i64, use VPOPCNTDQ instructions and truncate back. llvm-svn: 306990
* [X86][SSE] Attempt to combine 64-bit and 32-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-021-32/+21
| | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive llvm-svn: 306978
* [X86][SSE] Attempt to combine 64-bit and 16-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-021-64/+56
| | | | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive The 32-bit shuffles are a bit tricky and will be dealt with in a later patch llvm-svn: 306977
* [X86][CM] update add\sub costs of vectors of 64 in X86\SLM archMohammed Agabaria2017-07-021-4/+9
| | | | | | | | | this patch updates the cost of addq\subq (add\subtract of vectors of 64bits) based on the performance numbers of SLM arch. Differential Revision: https://reviews.llvm.org/D33983 llvm-svn: 306974
* [GlobalISel][X86] Support G_GLOBAL_VALUE operation.Igor Breger2017-07-022-8/+64
| | | | | | | | | | | | | | | | | Summary: Support G_GLOBAL_VALUE operation. For now most of the PIC configurations not implemented yet. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34738 Conflicts: test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir llvm-svn: 306972
* [GlobalISel][X86] Support vector type G_UNMERGE_VALUES selection.Igor Breger2017-07-021-0/+31
| | | | | | | | | | | | | | | | Summary: Support vector type G_UNMERGE_VALUES selection. For now G_UNMERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Reviewers: t.p.northover, qcolombet, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33665 llvm-svn: 306971
* fix trivial typos; NFCHiroshi Inoue2017-07-023-3/+3
| | | | | | suport -> support llvm-svn: 306968
* Remove the default ARMSubtarget from the ARM TargetMachine.Eric Christopher2017-07-013-11/+20
| | | | | | | This enables us to ensure better LTO and code generation in the face of module linking. Remove a report_fatal_error from the TargetMachine and replace it with an assert in ARMSubtarget - and remove the test that depended on the error. The assertion will still fire in the case that we were reporting before, but error reporting needs to be in front end tools if possible for options parsing. llvm-svn: 306939
* Rewrite ARM execute only support to avoid the use of a command line flag and ↵Eric Christopher2017-07-014-29/+21
| | | | | | | | unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
* [AVR] Update AVRASmBackend from API change in r306906Dylan McKay2017-07-012-7/+7
| | | | llvm-svn: 306923
* [X86] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-07-012-47/+55
| | | | | | NFC llvm-svn: 306921
* [ARM] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-07-012-54/+63
| | | | | | NFC llvm-svn: 306920
* Rename and adjust processFixupValue.Rafael Espindola2017-06-306-38/+37
| | | | | | | It was not processing any value. All that it ever did was force relocations, so name it shouldForceRelocation. llvm-svn: 306906
* [Hexagon] Implement frame pointer elimination with -fomit-frame-pointerKrzysztof Parzyszek2017-06-303-119/+156
| | | | | | | It applies to leaf functions that are otherwise not required to have a frame pointer. llvm-svn: 306888
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-302-0/+11
| | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table generated from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306877
* [SystemZ] Add all remaining instructionsUlrich Weigand2017-06-3015-132/+1169
| | | | | | | | | | | This adds all remaining instructions that were still missing, mostly privileged and semi-privileged system-level instructions. These are provided for use with the assembler and disassembler only. This brings the LLVM assembler / disassembler to parity with the GNU binutils tools. llvm-svn: 306876
* GlobalISel: add G_IMPLICIT_DEF instruction.Tim Northover2017-06-301-0/+3
| | | | | | | | | It looks like there are two target-independent but not GISel instructions that need legalization, IMPLICIT_DEF and PHI. These are already anomalies since their operands have important LLTs attached, so to make things more uniform it seems like a good idea to add generic variants. Starting with G_IMPLICIT_DEF. llvm-svn: 306875
* [Hexagon] Emit jump tables in text section based on a flagSumanth Gundapaneni2017-06-302-0/+12
| | | | | | | | This patch adds a new LLVM flag -hexagon-emit-jt-text which is defaulted to "false". The value "true" emits the switch generated jump tables in text section. Differential Revision: https://reviews.llvm.org/D34820 llvm-svn: 306872
* Revert "[Hexagon] Guard the generation of lookup table"Sumanth Gundapaneni2017-06-302-12/+0
| | | | | | | This reverts commit ae521f4192c3ed0202c047fec993cb59133dd1a0. Wrong commit message llvm-svn: 306871
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-302-0/+12
| | | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306869
* ARM: fix big-endian 64-bit cmpxchg.Tim Northover2017-06-301-4/+11
| | | | | | | | | | On big-endian machines the high and low parts of the value accessed by ldrexd and strexd are swapped around. To account for this we swap inputs and outputs in ISelLowering. Patch by Bharathi Seshadri. llvm-svn: 306865
* Make 0 argument getSubtargetImpl functions for the X86, AArch64, and PPC ↵Eric Christopher2017-06-303-0/+3
| | | | | | targets deleted so that no one is tempted to use them. llvm-svn: 306864
* [X86][SSE] Pulled common variables to top of matchUnaryPermuteVectorShuffle. ↵Simon Pilgrim2017-06-301-5/+4
| | | | | | NFCI. llvm-svn: 306847
* [MIPS] Handle PIC load address macro instructions in N64.Simon Dardis2017-06-301-0/+80
| | | | | | | | | | | | | | | | | | | | In particular, use CALL16 (similar to O32) for address loads into T9 for certain cases. Otherwise use a %got_disp relocation to load the address of a symbol. Small offsets (small enough to fit in a 16-bit signed immediate) can be used and are added to the symbol address after it is loaded from the GOT. Larger offsets are currently unsupported and result in an error from the assembler. Reviewers: sdardis Reviewed By: sdardis Patch by: John Baldwin Subscribers: llvm-commits, seanbruno, arichardson, emaste, dim Differential Revision: https://reviews.llvm.org/D33948 llvm-svn: 306831
* [SystemZ] Add missing high-word facility instructionsUlrich Weigand2017-06-305-0/+70
| | | | | | | | | | | There are a few instructions provided by the high-word facility (z196) that we cannot easily exploit for code generation. This patch at least adds those missing instructions for the assembler and disassembler. This means that now all nonprivileged instructions up to z13 are supported by the LLVM assembler / disassembler. llvm-svn: 306821
* fix trivial typos, NFCHiroshi Inoue2017-06-301-1/+1
| | | | llvm-svn: 306808
* [GlobalISel] Make multi-step legalization work.Kristof Beyls2017-06-301-38/+1
| | | | | | | | | | | | | | | | In r301116, a custom lowering needed to be introduced to be able to legalize 8 and 16-bit divisions on ARM targets without a division instruction, since 2-step legalization (WidenScalar from 8 bit to 32 bit, then Libcall the 32-bit division) doesn't work. This fixes this and makes this kind of multi-step legalization, where first the size of the type needs to be changed and then some action is needed that doesn't require changing the size of the type, straighforward to specify. Differential Revision: https://reviews.llvm.org/D32529 llvm-svn: 306806
* fix trivial typo; NFCHiroshi Inoue2017-06-301-1/+1
| | | | llvm-svn: 306798
* [WebAssembly] Add support for exception handling instructionsHeejin Ahn2017-06-301-5/+21
| | | | | | | | | | | | | | | | | | | Summary: This adds backend support for throw, rethrow, try, and try_end instructions. This needs the corresponding clang builtin support: https://reviews.llvm.org/D34783 This follows the Wasm exception handling proposal in https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md Reviewers: sunfish, dschuff Reviewed By: dschuff Subscribers: jfb, sbc100, jgravelle-google Differential Revision: https://reviews.llvm.org/D34826 llvm-svn: 306774
* Unified logic for computing target ABI in backend and front end by moving ↵Eric Christopher2017-06-301-50/+10
| | | | | | | | | | this common code to Support/TargetParser. Modeled Triple::GNU after front end code (aapcs abi) and updated tests that expect apcs abi. Based heavily on a patch by Ana Pazos! llvm-svn: 306768
* To help readability of mightUseCTR pull out the inline asm handling support ↵Eric Christopher2017-06-291-10/+17
| | | | | | into a function. llvm-svn: 306762
* Make the PPCCTRLoops pass depend on being able to access the TargetMachine ↵Eric Christopher2017-06-293-49/+36
| | | | | | and clean up accordingly. llvm-svn: 306761
* Revert "[mips] Fix multiprecision arithmetic."Simon Dardis2017-06-294-187/+226
| | | | | | | This reverts commit r305389. This broke chromium builds, so reverting while I investigate further. llvm-svn: 306741
* [AArch64] Silence an unused variable warning in Release builds. NFC.Chad Rosier2017-06-291-0/+1
| | | | llvm-svn: 306738
* [Hexagon] Keep all phi nodes when building DFG in addr-mode-optKrzysztof Parzyszek2017-06-291-4/+6
| | | | | | | The dead phis are needed for finding correct would-be reaching defs in register propagation. llvm-svn: 306690
* [llvm-objdump] Handle invalid instruction gracefully on ARMEugene Leviant2017-06-291-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D34813 llvm-svn: 306687
* bpf: remove unnecessary truncate operationYonghong Song2017-06-291-77/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For networking-type bpf program, it often needs to access packet data. A context data structure is provided to the bpf programs with two fields: u32 data; u32 data_end; User can access these two fields with ctx->data and ctx->data_end. During program verification process, the kernel verifier modifies the bpf program with loading of actual pointer value from kernel data structure. r = ctx->data ===> r = actual data start ptr r = ctx->data_end ===> r = actual data end ptr A typical program accessing ctx->data like char *data_ptr = (char *)(long)ctx->data will result in a 32-bit load followed by a zero extension. Such an operation is combined into a single LDW in DAG combiner as bpf LDW does zero extension automatically. In cases like the below (which can be a result of global value numbering and partial redundancy elimination before insn selection): B1: u32 a = load-32-bit &ctx->data u64 pa = zext a ... B2: u32 b = load-32-bit &ctx->data u64 pb = zext b ... B3: u32 m = PHI(a, b) u64 pm = zext m In B3, "pm = zext m" cannot be removed, which although is legal from compiler perspective, will generate incorrect code after kernel verification. This patch recognizes this pattern and traces through PHI node to see whether the operand of "zext m" is defined with LDWs or not. If it is, the "zext m" itself can be removed. The patch also recognizes the pattern where the load and use of the load value not in the same basic block, where truncate operation may be removed as well. The patch handles 1-byte, 2-byte and 4-byte truncation. Two test cases are added to verify the transformation happens properly for the above code pattern. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 306685
* [PowerPC] fix potential verification error on __tls_get_addrHiroshi Inoue2017-06-293-4/+22
| | | | | | | | | | This patch fixes a verification error with -verify-machineinstrs while expanding __tls_get_addr by not creating ADJCALLSTACKUP and ADJCALLSTACKDOWN if there is another ADJCALLSTACKUP in this basic block since nesting ADJCALLSTACKUP/ADJCALLSTACKDOWN is not allowed. Here, ADJCALLSTACKUP and ADJCALLSTACKDOWN are created as a fence for instruction scheduling to avoid _tls_get_addr is scheduled before mflr in the prologue (https://bugs.llvm.org//show_bug.cgi?id=25839). So if another ADJCALLSTACKUP exists before _tls_get_addr, we do not need to create a new ADJCALLSTACKUP. Differential Revision: https://reviews.llvm.org/D34347 llvm-svn: 306678
* Revert "r306529 - [X86] Correct dwarf unwind information in function epilogue"Daniel Jasper2017-06-293-131/+8
| | | | | | | | | | I am 99% sure that this breaks the PPC ASAN build bot: http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/3112/steps/64-bit%20check-asan/logs/stdio If it doesn't go back to green, we can recommit (and fix the original commit message at the same time :) ). llvm-svn: 306676
* [TargetTransformInfo, API] Add a list of operands to TTI::getUserCostEvgeny Astigeevich2017-06-292-4/+5
| | | | | | | | | | | | | | | | | | | | The changes are a result of discussion of https://reviews.llvm.org/D33685. It solves the following problem: 1. We can inform getGEPCost about simplified indices to help it with calculating the cost. But getGEPCost does not take into account the context which GEPs are used in. 2. We have getUserCost which can take the context into account but we cannot inform about simplified indices. With the changes getUserCost will have access to additional information as getGEPCost has. The one parameter getUserCost is also provided. Differential Revision: https://reviews.llvm.org/D34057 llvm-svn: 306674
* [GlobalISel][X86] Support vector type G_MERGE_VALUES selection.Igor Breger2017-06-291-0/+53
| | | | | | | | | | | | | | | | Summary: Support vector type G_MERGE_VALUES selection. For now G_MERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33958 llvm-svn: 306665
* [LLVM][X86][Goldmont] Adding new target-cpu: GoldmontMichael Zuckerman2017-06-292-1/+31
| | | | | | | | | | | | | | | | [LLVM SIDE] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. zvi 3. delena 4. RKSimon 5. craig.topper Differential Revision: https://reviews.llvm.org/D34504 llvm-svn: 306658
* [ARM] Add tGPRwithpc register class and use it for TBB/THHFlorian Hahn2017-06-292-4/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: TBB and THH allow using a Thumb GPR or the PC as destination operand. A few machine verifier failures where due to those instructions not expecting PC as destination operand. Add -verify-machineinstrs to test/CodeGen/ARM/jump-table-tbh.ll to add test coverage even if expensive checks are disabled. Reviewers: MatzeB, t.p.northover, jmolloy Reviewed By: MatzeB Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34610 llvm-svn: 306654
* AMDGPU: Remove SITypeRewriterMatt Arsenault2017-06-284-159/+0
| | | | | | | This was an old workaround for using v16i8 in some old intrinsics for resource descriptors. llvm-svn: 306603
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