summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Don't repeat names in comments and clang-format this function.Rafael Espindola2015-03-161-7/+10
| | | | llvm-svn: 232375
* [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.Daniel Sanders2015-03-162-5/+8
| | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 llvm-svn: 232374
* Make each target map all inline assembly memory constraints to ↵Daniel Sanders2015-03-1611-0/+67
| | | | | | | | | | | | | | | | | | | InlineAsm::Constraint_m. NFC. Summary: This is instead of doing this in target independent code and is the last non-functional change before targets begin to distinguish between different memory constraints when selecting code for the ISD::INLINEASM node. Next, each target will individually move away from the idea that all memory constraints behave like 'm'. Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8173 llvm-svn: 232373
* [mips] [IAS] Outline NOP creation. NFC.Toma Tabacu2015-03-161-22/+26
| | | | | | | | | | | | | | Summary: Make the code more readable by outlining NOP creation. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8320 llvm-svn: 232371
* [llvm] Replacing asserts with static_asserts where appropriateGabor Horvath2015-03-162-2/+3
| | | | | | | | | | | | | | | | Summary: This patch consists of the suggestions of clang-tidy/misc-static-assert check. Reviewers: alexfh Reviewed By: alexfh Subscribers: xazax.hun, llvm-commits Differential Revision: http://reviews.llvm.org/D8343 llvm-svn: 232366
* Use SDValue bool check to tidyup some possible combines. NFC.Simon Pilgrim2015-03-151-4/+2
| | | | llvm-svn: 232331
* Use SDValue bool check to tidyup some possible combines. NFC.Simon Pilgrim2015-03-151-5/+3
| | | | llvm-svn: 232325
* [opaque pointer type] gep API migrationDavid Blaikie2015-03-141-5/+6
| | | | llvm-svn: 232279
* [opaque pointer type] more gep API migrationDavid Blaikie2015-03-141-4/+3
| | | | llvm-svn: 232274
* [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.Vasileios Kalintiris2015-03-144-60/+20
| | | | llvm-svn: 232260
* [mips] Remove trivial header for the Mips16HardFloat pass. NFC.Vasileios Kalintiris2015-03-144-129/+97
| | | | llvm-svn: 232259
* [mips] Remove trivial header for the MipsOs16 pass. NFC.Vasileios Kalintiris2015-03-144-93/+72
| | | | llvm-svn: 232258
* Use add32ri8 and friends on fast isel.Rafael Espindola2015-03-131-5/+5
| | | | | | | | | | | | | | | This fixes pr22854. The core issue on the bug is that there are multiple instructions that print the same in assembly. In fact, there doesn't seem to be any syntax for specifying that a constant that fits in 8 bits should use a 32 bit immediate. The attached patch changes fast isel to consider i16immSExt8, i32immSExt8, and i64immSExt8. They were disabled because fastisel didn’t know to call the predicate back in the day. llvm-svn: 232223
* bpf: turn on HasJIT flag in BPF backendAlexei Starovoitov2015-03-131-1/+1
| | | | | | basic tests that use BPF backend to produce code in memory are passing. llvm-svn: 232222
* bpf: fix buildAlexei Starovoitov2015-03-133-3/+0
| | | | | | | fix missed bits which were left over after r231987 Signed-off-by: Alexei Starovoitov <ast@plumgrid.com> llvm-svn: 232208
* r600: Clear visited structure before running.Jan Vesely2015-03-131-0/+1
| | | | | | | | Fixes random crashes in for-loop piglit. Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 232181
* r600: Use deque and simplify loops in AMDGPUCFGStructurizerJan Vesely2015-03-131-10/+10
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 232180
* [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus ↵Andrea Di Biagio2015-03-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | extract_subvector nodes. This patch fixes a bug in the shuffle lowering logic implemented by function 'lowerV2X128VectorShuffle'. The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR nodes. The problematic expansion only occurs when the shuffle mask M has an 'undef' element at position 2, and M is equivalent to mask <0,1,4,5>. In that case, the algorithm propagates the wrong vector to one of the two new EXTRACT_SUBVECTOR nodes. Example: ;; define <4 x double> @test(<4 x double> %A, <4 x double> %B) { entry: %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5> ret <4 x double> %0 } ;; Before this patch, llc (-mattr=+avx) generated: vinsertf128 $1, %xmm0, %ymm0, %ymm0 With this patch, llc correctly generates: vinsertf128 $1, %xmm1, %ymm0, %ymm0 Added test lower-vec-shuffle-bug.ll Differential Revision: http://reviews.llvm.org/D8259 llvm-svn: 232179
* unique_ptrs are unique already, no need to unique them any further.Benjamin Kramer2015-03-131-8/+7
| | | | llvm-svn: 232178
* Recommit r232027 with PR22883 fixed: Add infrastructure for support of ↵Daniel Sanders2015-03-1316-43/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | multiple memory constraints. The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. llvm-svn: 232165
* [mips] [IAS] Refactor MipsTargetStreamer::emitMipsAbiFlags(). NFC.Toma Tabacu2015-03-132-7/+1
| | | | | | | | | | | | | | Summary: Make emitMipsAbiFlags a direct member of MipsTargetELFStreamer, as that's the only place where it's used, and remove the empty implementations from MipsTargetStreamer and MipsTargetAsmStreamer. Reviewers: dsanders, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D8199 llvm-svn: 232161
* [X86, AVX2] Replace inserti128 and extracti128 intrinsics with generic shufflesSanjay Patel2015-03-121-3/+1
| | | | | | | | | | | | | | | | | This should complete the job started in r231794 and continued in r232045: We want to replace as much custom x86 shuffling via intrinsics as possible because pushing the code down the generic shuffle optimization path allows for better codegen and less complexity in LLVM. AVX2 introduced proper integer variants of the hacked integer insert/extract C intrinsics that were created for this same functionality with AVX1. This should complete the removal of insert/extract128 intrinsics. The Clang precursor patch for this change was checked in at r232109. llvm-svn: 232120
* Move a variable into the assert where it's used - fixes a -AssertsEric Christopher2015-03-121-2/+1
| | | | | | build warning/error. llvm-svn: 232119
* In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher2015-03-1212-146/+105
| | | | | | | merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. llvm-svn: 232117
* R600/SI: Don't print scc reg in sopc assembly stringTom Stellard2015-03-121-1/+1
| | | | | | This is how the proprietary driver prints sopc instructions. llvm-svn: 232106
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-125-25/+41
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* Migrate the AArch64 TargetRegisterInfo to its TargetMachineEric Christopher2015-03-128-48/+52
| | | | | | | implementation. This requires a bit of scaffolding and a few fixups that'll go away once all of the ports have been migrated. llvm-svn: 232103
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-1213-45/+41
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* [X86] Fix a regression introduced by r223641.Quentin Colombet2015-03-122-2/+7
| | | | | | | | | | | | | The permps and permd instructions have their operands swapped compared to the intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP category. I did not create a new category for those two, as they are the only one AFAICT in that case. <rdar://problem/20108262> llvm-svn: 232085
* Fix comment formatting.Eric Christopher2015-03-121-2/+1
| | | | llvm-svn: 232076
* Remove the need to cache the subtarget in the X86 TargetRegisterInfoEric Christopher2015-03-123-24/+23
| | | | | | | classes. Use a Triple instead and simplify a lot of the querying logic to use lookups on the Triple. llvm-svn: 232071
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-127-611/+215
| | | | llvm-svn: 232057
* [X86] Fix wrong target specific combine on SETCC nodes.Andrea Di Biagio2015-03-121-26/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the folding logic implemented by function 'PerformISDSETCCCombine' only worked under the assumption that the condition code in input could have been either SETNE or SETEQ. Unfortunately that assumption was incorrect, and in some cases the algorithm ended up incorrectly folding SETCC nodes. The incorrect folding only affected SETCC dag nodes where: - one of the operands was a build_vector of all zeroes; - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements; - the condition code was neither SETNE nor SETEQ. Example: (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge) Before this patch, the entire dag node sequence from the example was incorrectly folded to node %A. With this patch, the dag node sequence is folded to a (xor %A, (v4i1 VectorOfAllOnes)). Added test setcc-combine.ll. Thanks to Greg Bedwell for spotting this issue. llvm-svn: 232046
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2015-03-121-1/+1
| | | | | | warning; NFC. llvm-svn: 232035
* Add infrastructure for support of multiple memory constraints.Daniel Sanders2015-03-1213-41/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8171 llvm-svn: 232027
* AVX-512: Added encoding tests for VPROR, VPROL instructions,Elena Demikhovsky2015-03-121-2/+2
| | | | | | fixed opcode. llvm-svn: 232018
* Remove some unnecessary forward declarations and put a couple moreEric Christopher2015-03-128-24/+3
| | | | | | where they're supposed to reside. llvm-svn: 232014
* Remove the need to cache the subtarget in the Sparc TargetRegisterInfoEric Christopher2015-03-124-12/+11
| | | | | | classes. llvm-svn: 232013
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-1210-26/+26
| | | | | | classes. llvm-svn: 232012
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-1211-44/+39
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Remove the need to cache the subtarget in the AArch64 TargetRegisterInfoEric Christopher2015-03-124-21/+26
| | | | | | | classes. Replace it with a cache to the Triple and use that where applicable at the moment. llvm-svn: 232005
* [NVPTXAsmPrinter] do not print .align on function headersJingyue Wu2015-03-121-0/+2
| | | | | | | | | | | | | | | | | | | Summary: PTX does not allow .align directives on function headers. Fixes PR21551. Test Plan: test/Codegen/NVPTX/function-align.ll Reviewers: eliben, jholewinski Reviewed By: eliben, jholewinski Subscribers: llvm-commits, eliben, jpienaar, jholewinski Differential Revision: http://reviews.llvm.org/D8274 llvm-svn: 232004
* Remove the need to cache the subtarget in the PowerPC TargetRegisterInfoEric Christopher2015-03-123-55/+68
| | | | | | | classes. Replace it with a cache to the TargetMachine and use that where applicable at the moment. llvm-svn: 232002
* Fix build break introduced in r231992Krzysztof Parzyszek2015-03-121-4/+2
| | | | llvm-svn: 231996
* Eliminate constant-extender profitability checks from Hexagon iselKrzysztof Parzyszek2015-03-127-515/+225
| | | | llvm-svn: 231992
* Move the DataLayout to the generic TargetMachine, making it mandatory.Mehdi Amini2015-03-1228-93/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231987
* [PowerPC] Remove canFoldAsLoad from instruction definitionsHal Finkel2015-03-115-8/+8
| | | | | | | | | | | | | | | | | The PowerPC backend had a number of loads that were marked as canFoldAsLoad (and I'm partially at fault here for copying around the relevant line of TableGen definitions without really looking at what it meant). This is not right; PPC (non-memory) instructions don't support direct memory operands, and so there is nothing a 'foldable' instruction could be folded into. Noticed by inspection, no test case. The one thing we might lose by doing this is ability to fold some loads into stackmap/patchpoint pseudo-instructions. However, this was untested, and would not obviously have worked for extending loads, and I'd rather re-add support for that once it can be tested. llvm-svn: 231982
* Remove useMachineScheduler and replace it with subtarget optionsEric Christopher2015-03-114-30/+20
| | | | | | | | | | | | | that control, individually, all of the disparate things it was controlling. At the same time move a FIXME in the Hexagon port to a new subtarget function that will enable a user of the machine scheduler to avoid using the source scheduler for pre-RA-scheduling. The FIXME would have this removed, but involves either testcase changes or adding -pre-RA-sched=source to a few testcases. llvm-svn: 231980
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-1126-50/+73
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* One more getCalleeSavedRegs prototype with nullptr.Eric Christopher2015-03-111-2/+1
| | | | llvm-svn: 231977
OpenPOWER on IntegriCloud