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* [x86] allow 64-bit extracted vector element integer stores on a 32-bit systemSanjay Patel2015-04-221-0/+21
| | | | | | | | | | | | | | | | | | | | | With SSE2, we can generate a 'movq' or other 64-bit store op on a 32-bit system even though 64-bit integers are not legal types. So instead of producing this: pshufd $229, %xmm0, %xmm1 ## xmm1 = xmm0[1,1,2,3] movd %xmm0, (%eax) movd %xmm1, 4(%eax) We can do: movq %xmm0, (%eax) This is a fix for the problem noted in D7296. Differential Revision: http://reviews.llvm.org/D9134 llvm-svn: 235460
* [Hexagon] Patterns for frame index with offset for iselKrzysztof Parzyszek2015-04-211-0/+1
| | | | llvm-svn: 235418
* [NVPTX] do not run DCE after SLSR and SeparateConstOffsetFromGEPJingyue Wu2015-04-211-10/+4
| | | | | | | | | | | | | | | | Summary: With D9096 and D9101, there's no need to run DCE after SLSR and SeparateConstOffsetFromGEP. Test Plan: no regression Reviewers: jholewinski, meheff Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D9172 llvm-svn: 235415
* X86: Match for X86ISD nodes in LowerBUILD_VECTOR instead of BUILD_VECTORCombineMatthias Braun2015-04-211-24/+23
| | | | | | | | | There doesn't seem to be a reason to perform this target ISD node matching in an DAGCombine, moving it to lowering fixes PR23296. Differential Revision: http://reviews.llvm.org/D9137 llvm-svn: 235394
* AVX-512: Added VPMOVx2M instructions for SKX,Elena Demikhovsky2015-04-211-1/+30
| | | | | | fixed encoding of VPMOVM2x. llvm-svn: 235385
* AVX-512: Added VPTESTM and VPTESTNM instructions for SKXElena Demikhovsky2015-04-212-30/+127
| | | | llvm-svn: 235383
* [mips] [IAS] Implement the .asciiz directive.Toma Tabacu2015-04-211-0/+2
| | | | | | | | | | | | | | | | Summary: This directive is exactly the same as .asciz, except it's only used by MIPS. It is used to store null terminated strings in object files. Reviewers: rafael, dsanders, echristo Reviewed By: dsanders, echristo Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D7530 llvm-svn: 235382
* [mips][microMIPSr6] Implement CACHE and PREF instructionsJozef Kolek2015-04-213-3/+32
| | | | | | | | Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
* [mips] Cleanup old floating-point flag conditions definitions. NFC.Vasileios Kalintiris2015-04-211-22/+0
| | | | | | | | Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7947 llvm-svn: 235377
* [mips] Optimize code generation for 64-bit variable shift instructions.Vasileios Kalintiris2015-04-211-0/+10
| | | | | | | | | | | | | | | | Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
* AVX-512: Added logical and arithmetic instructions for SKXElena Demikhovsky2015-04-213-82/+178
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 235375
* [X86][SSE] Provide execution domains for scalar floating point operationsSimon Pilgrim2015-04-211-38/+41
| | | | | | | | | | This is an updated version of Chandler's patch D7402 that got accepted but never committed, and has bit-rotted a bit since. I've updated the execution domain declarations to match the approach of the packed templates and also added some extra scalar unary tests. Differential Revision: http://reviews.llvm.org/D9095 llvm-svn: 235372
* X86: Do not select X86 custom vector nodes if operand types don't matchMatthias Braun2015-04-211-4/+16
| | | | | | | | | | | | | X86ISD::ADDSUB, X86ISD::(F)HADD, X86ISD::(F)HSUB should not be selected if the operand types do not match the result type because vector type legalization cannot deal with this for custom nodes. Testcase X86ISD::ADDSUB is attached. I could not create a testcase for the FHADD/FHSUB cases because of: https://llvm.org/bugs/show_bug.cgi?id=23296 Differential Revision: http://reviews.llvm.org/D9120 llvm-svn: 235367
* [MIPS] OperationAction for FP_TO_FP16, FP16_TO_FPPirama Arumuga Nainar2015-04-201-2/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: Set operation action for FP16 conversion opcodes, so the Op legalizer can choose the gnu_* libcalls for Mips. Set LoadExtAction and TruncStoreAction for f16 scalars and vectors to prevent (fpext (load )) and (store (fptrunc)) from getting combined into unsupported operations. Added test cases to test that these operations are handled correctly for f16 scalars and vectors. This patch depends on http://reviews.llvm.org/D8755. Reviewers: srhines Subscribers: llvm-commits, ab Differential Revision: http://reviews.llvm.org/D8804 llvm-svn: 235341
* [mips][microMIPSr6] Implement BITSWAP instructionJozef Kolek2015-04-203-2/+30
| | | | | | | | Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
* [AArch64] LORID_EL1 register must be treated as read-onlyVladimir Sukharev2015-04-201-3/+5
| | | | | | | | | | | | Patch by: John Brawn Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9105 llvm-svn: 235314
* [PowerPC] Flow oversized lines for r235309Bill Schmidt2015-04-201-11/+25
| | | | llvm-svn: 235310
* [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txtBill Schmidt2015-04-201-0/+14
| | | | llvm-svn: 235309
* [mips][microMIPSr6] Implement disassembler supportJozef Kolek2015-04-202-4/+13
| | | | | | | | Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
* [mips][microMIPSr6] Implement BALC and BC instructionsJozef Kolek2015-04-203-3/+58
| | | | | | | | This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
* [mips][microMIPSr6] Implement initial mapping supportJozef Kolek2015-04-203-2/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D8387 llvm-svn: 235298
* [mips][microMIPSr6] Implement initial subtarget supportJozef Kolek2015-04-204-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D8386 llvm-svn: 235296
* [X86][FastIsel] Fix assertion failure when selecting int-to-double ↵Andrea Di Biagio2015-04-201-5/+6
| | | | | | | | | | | | | | | | | | | | | | conversion (PR23273). This fixes a regression introduced at revision 231243. The target-independent selection algorithm in FastISel knows how to select a SINT_TO_FP if the target is SSE but not AVX. That is because on X86, the tablegen'd 'fastEmit' functions know how to select CVTSI2SSrr and CVTSI2SDrr. Method X86FastISel::X86SelectSIToFP was therefore working under the wrong assumption that the target was AVX. That assumption was incorrect since we can have a target that is neither AVX nor SSE. So, rather than asserting for the presence of AVX, we should have had an early exit from 'X86SelectSIToFP' if the target was not AVX. This patch fixes the issue replacing the invalid assertion with an early exit. Thanks to Dimitry Andric for reporting this problem and for providing a small reproducible testcase. Added test pr23273.ll. llvm-svn: 235295
* [X86][SSE] Fix for getScalarValueForVectorElement to detect scalar sources ↵Simon Pilgrim2015-04-191-2/+7
| | | | | | | | | | requiring truncation. The fix ensures that scalar sources inserted into a vector are the correct bit size. Integer scalar sources from BUILD_VECTOR and SCALAR_TO_VECTOR nodes may require truncation that this function doesn't currently support. llvm-svn: 235281
* Remove unnecessary include and probably a layering violation.Craig Topper2015-04-191-1/+0
| | | | llvm-svn: 235262
* [AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.Ahmed Bougacha2015-04-171-1/+1
| | | | | | | | | | | | | | | | | | | The result is either an Untyped reg sequence, on ldN with N > 1, or just the type of the input vector, on ld1. Don't force Untyped. Instead, just use the type of the reg sequence. This mirrors the behavior of createTuple, which feeds the LD1*_POST. The narrow code path wasn't actually covered by tests, because V64 insert_vector_elt are widened to V128 before the LD1LANEpost combine has the chance to run, usually. The only case where it does run on V64 vectors is if the vector ops legalizer ran. So, tickle the code with a ctpop. Fixes PR23265. llvm-svn: 235243
* [AArch64] Avoid vector->load dependency cycles when creating LD1*post.Ahmed Bougacha2015-04-171-0/+7
| | | | | | | | They would break the SelectionDAG. Note that the opposite load->vector dependency is already obvious in: (LD1*post vec, ..) llvm-svn: 235224
* [mips][FastISel] Implement FastMaterializeAlloca in Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+20
| | | | | | | | | | | | | | | | | | Summary: Implement the method FastMaterializeAlloca in Mips fast-isel Based on a patch by Reed Kotler. Test Plan: Passes test-suite at O0/O2 for mips32 r1/r2 fastalloca.ll Reviewers: dsanders, rkotler Subscribers: rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6742 llvm-svn: 235213
* [X86, AVX] add an exedepfix entry for vmovq == vmovlps == vmovlpdSanjay Patel2015-04-171-1/+1
| | | | | | | | | | This is the AVX extension of r235014: http://llvm.org/viewvc/llvm-project?view=revision&revision=235014 Review: http://reviews.llvm.org/D8691 llvm-svn: 235210
* [mips][FastISel] Implement shift ops for Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+80
| | | | | | | | | | | | | | | | | | Summary: Add shift operators implementation to fast-isel for Mips. These are shift ops for non legal forms, i.e. i8 and i16. Based on a patch by Reed Kotler. Test Plan: Reviewers: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6726 llvm-svn: 235194
* Move AliasedSymbol to MachObjectWriter.Rafael Espindola2015-04-171-2/+2
| | | | | | | It was only used by MachO. Part of pr19627. llvm-svn: 235185
* [mips] Teach the delay slot filler to remove needless KILL instructions.Vasileios Kalintiris2015-04-171-11/+30
| | | | | | | | | | | | | | | | | | Summary: Previously, the presence of KILL instructions would block valid candidates from filling a specific delay slot. With the elimination of the KILL instructions, in the appropriate range, we are able to fill more slots and keep the information from future def/use analysis consistent. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D7724 llvm-svn: 235183
* [mc] Clean up emission of byte sequencesBenjamin Kramer2015-04-174-18/+4
| | | | | | No functional change intended. llvm-svn: 235178
* [mips] Move ABI-dependent register selections to MipsABIInfo. NFC.Daniel Sanders2015-04-176-49/+84
| | | | | | | | | | | | | | | | | | | | | Summary: For example, a common idiom was 'isN64 ? Mips::SP_64 : Mips::SP'. This has been moved to MipsABIInfo and replaced with 'ABI.GetStackPtr()'. There are others that should also be moved. This patch sticks to the ones that are obviously non-functional. The others have minor mistakes that need fixing at the same time, mostly involving checks for 64-bit GPR's instead of checks for 64-bit pointers. Reviewers: tomatabacu Reviewed By: tomatabacu Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8972 llvm-svn: 235173
* [AArch64] Don't assert on f16 in DUP PerfectShuffle generator.Ahmed Bougacha2015-04-161-1/+1
| | | | | | | | Found by code inspection, but breaking i16 at least breaks other tests. They aren't checking this in particular though, so also add some explicit tests for the already working types. llvm-svn: 235148
* Disable AArch64 fast-isel on big-endian call vector returns.Pete Cooper2015-04-161-0/+5
| | | | | | | | A big-endian vector return needs a byte-swap which we aren't doing right now. For now just bail on these cases to get correctness back. llvm-svn: 235133
* [AArch64] Add v8.1a "Virtualization Host Extensions"Vladimir Sukharev2015-04-162-1/+59
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8500 Patch by: Tom Coxon llvm-svn: 235107
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-165-0/+40
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8499 Patch by: Tom Coxon llvm-svn: 235105
* [AArch64] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-162-3/+18
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8498 llvm-svn: 235104
* [AArch64] Handle Cyclone-specific register in common wayVladimir Sukharev2015-04-162-29/+5
| | | | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8584 Patch by: Tom Coxon llvm-svn: 235102
* [AArch64] Follow-up to: Refactor AArch64NamedImmMapper to become dependent ↵Vladimir Sukharev2015-04-161-665/+665
| | | | | | | | | | on subtarget features Fixed compilation with clang on some buildbots with "-Werror -Wmissing-field-initializers" Related to: http://reviews.llvm.org/rL235089 llvm-svn: 235099
* [mips] [IAS] Preserve microMIPS label marking for objects when assigning.Toma Tabacu2015-04-161-3/+2
| | | | | | | | | | | | | | Summary: Previously, this was only happening for functions, but because of .insn, objects can also be marked now. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8007 llvm-svn: 235095
* [Mips] Use unique_ptr to manage ownership.Benjamin Kramer2015-04-162-17/+10
| | | | | | | Required some tweaking of ValueMap to accommodate a move-only value type. No functional change intended. llvm-svn: 235091
* Make it obvious that we're iterating over a range of pointers.Benjamin Kramer2015-04-161-1/+1
| | | | | | Found by -Wrange-loop-analysis. llvm-svn: 235090
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-165-20/+46
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* [AArch64] Fix invalid use of references to BuildMI.James Molloy2015-04-161-3/+3
| | | | | | | | This was found in GCC PR65773 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65773). We shouldn't be taking a reference to the temporary that BuildMI returns, we must copy it. llvm-svn: 235088
* [ARM] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-164-3/+99
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
* [mips] [IAS] Add support for the .insn directive.Toma Tabacu2015-04-165-2/+47
| | | | | | | | | | | | | | | | | Summary: This assembler directive marks the current label as an instruction label in microMIPS and MIPS16. This initial implementation works only for microMIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8006 llvm-svn: 235084
* DebugInfo: Gut DIScope, DIEnumerator and DISubrangeDuncan P. N. Exon Smith2015-04-161-3/+3
| | | | | | The only class the still has API left is `DIDescriptor` itself. llvm-svn: 235067
* DebugInfo: Gut DICompileUnit and DIFileDuncan P. N. Exon Smith2015-04-151-3/+3
| | | | | | | Continuing gutting `DIDescriptor` subclasses; this edition, `DICompileUnit` and `DIFile`. In the name of PR23080. llvm-svn: 235055
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