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* [X86] Improve pfm counter coverage for llvm-exegesisSimon Pilgrim2018-12-071-0/+83
| | | | | | | | | | | | | | This patch attempts to improve pfm perf counter coverage for all the x86 CPUs that libpfm4 supports. Intel/AMD CPU families tend to share names for cycle/uops counters so even if they don't have a scheduler model yet they can at least use the default values (checked against the libpfm4 source code). The remaining CPUs (where their port/pipe resource counters are known) I've tried to add to the existing model mappings. These are untested but don't represent a regression to current llvm-exegesis behaviour for these CPUs. Differential Revision: https://reviews.llvm.org/D55432 llvm-svn: 348617
* AMDGPU: Remove llvm.SI.buffer.load.dwordMatt Arsenault2018-12-072-62/+0
| | | | llvm-svn: 348616
* AMDGPU: Remove llvm.AMDGPU.killMatt Arsenault2018-12-075-35/+5
| | | | | | This is the last of the old AMDGPU intrinsics. llvm-svn: 348615
* [AMDGPU] Shrink scalar AND, OR, XOR instructionsGraham Sellers2018-12-071-0/+84
| | | | | | | | | | | | | | | This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable. It performs: AND s0, s0, ~(1 << n) -> BITSET0 s0, n OR s0, s0, (1 << n) -> BITSET1 s0, n AND s0, s1, x -> ANDN2 s0, s1, ~x OR s0, s1, x -> ORN2 s0, s1, ~x XOR s0, s1, x -> XNOR s0, s1, ~x In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31). llvm-svn: 348601
* ARM: use correct offset from base pointer (r6) in call frame regions.Tim Northover2018-12-071-0/+1
| | | | | | | | | When we had dynamic call frames (i.e. sp adjustment around each call) we were including that adjustment into offsets calculated based on r6, even though it's only sp that changes. This led to incorrect stack slot accesses. llvm-svn: 348591
* [Targets] Add errors for tiny and kernel codemodel on targets that don't ↵David Green2018-12-0719-119/+69
| | | | | | | | | | | support them Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls. Differential Revision: https://reviews.llvm.org/D50141 llvm-svn: 348585
* Fix gcc7.3 -Wparentheses warning. NFCI.Simon Pilgrim2018-12-071-3/+3
| | | | llvm-svn: 348581
* [X86] Add ivybridge to llvm-exegesis PFM counter mappingsSimon Pilgrim2018-12-071-0/+1
| | | | llvm-svn: 348575
* [PowerPC] Fix assert from machine verify pass that missing undef register flagZi Xuan Wu2018-12-071-15/+11
| | | | | | | | | | | | | | | | | | | | Fix assert about using an undefined physical register in machine instruction verify pass. The reason is that register flag undef is missing when doing transformation from If Conversion Pass. ``` Bad machine code: Using an undefined physical register - function: func_65 - basic block: %bb.0 entry (0x10024740738) - instruction: BCLR killed $cr5lt, implicit $lr8, implicit $rm, implicit undef $x3 - operand 0: killed $cr5lt LLVM ERROR: Found 1 machine code errors. ``` There are also other existing testcases with same issue. So I add -verify-machineinstrs option to open verifying. Differential Revision: https://reviews.llvm.org/D55408 llvm-svn: 348566
* [X86] Directly create ADC/SBB nodes instead of using ADD/SUB with (and ↵Craig Topper2018-12-062-47/+8
| | | | | | | | | | | | SETCC_CARRY, 1) This addresses a FIXME and avoids depending on an isel pattern match I think. I've remove the isel patterns too since he have no lit tests left that cover them. Hopefully that really means they are unused. I'm trying to decide if we need SETCC_CARRY. This removes one of its usages. Differential Revision: https://reviews.llvm.org/D55355 llvm-svn: 348536
* [AArch64] Fix Exynos predicateEvandro Menezes2018-12-061-8/+10
| | | | | | Fix predicate for arithmetic instructions with shift and/or extend. llvm-svn: 348510
* [X86] Refactored IsSplatVector to use switch. NFCI.Simon Pilgrim2018-12-061-21/+24
| | | | | | | | Initial step towards making the function more generic (and probably move into SelectionDAG). This is necessary to avoid massive codegen bloat for PR38243 (Add modulo rotate support to LowerRotate). llvm-svn: 348498
* [DEBUGINFO, NVPTX] Disable emission of ',debug' option if only debug ↵Alexey Bataev2018-12-061-1/+15
| | | | | | | | | | | | | | | | | directives are allowed. Summary: If the output of debug directives only is requested, we should drop emission of ',debug' option from the target directive. Required for supporting of nvprof profiler. Reviewers: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46061 llvm-svn: 348497
* [DEBUGINFO, NVPTX]Emit last debugging directives.Alexey Bataev2018-12-063-3/+15
| | | | | | | | | | | | | | | Summary: We may end up with not emitted debug directives at the end of the module emission. Patch fixes this problem emitting those last directives the end of the module emission. Reviewers: echristo Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D54320 llvm-svn: 348495
* [NFC][AArch64] Split out backend featuresDiogo N. Sampaio2018-12-066-72/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits backend features currently hidden behind architecture versions. For example, currently the only way to activate complex numbers extension is targeting an v8.3 architecture, where after the patch this extension can be added separately. This refactoring is required by the new command lines proposal: http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html Reviewers: DavidSpickett, olista01, t.p.northover Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio Differential revision: https://reviews.llvm.org/D54633 -- It was reverted in rL348249 due a build bot failure in one of the regression tests: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14386 The problem seems to be that FileCheck behaves different in windows and linux. This new patch splits the test file in multiple, and does more exact pattern matching attempting to circumvent the issue. llvm-svn: 348493
* AMDGPU: Generate VALU ThreeOp Integer instructionsNicolai Haehnle2018-12-061-0/+47
| | | | | | | | | | | | | | | Summary: Original patch by: Fabian Wahlster <razor@singul4rity.com> Change-Id: I148f692a88432541fad468963f58da9ddf79fac5 Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, b-sumner, llvm-commits Differential Revision: https://reviews.llvm.org/D51995 llvm-svn: 348488
* [AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by defaultValery Pykhtin2018-12-061-1/+1
| | | | | | | | Turn the combiner back off as there're failures until the issue is fixed. Differential revision: https://reviews.llvm.org/D55314 llvm-svn: 348487
* [ARM GlobalISel] Nothing is legal for ThumbDiana Picus2018-12-061-0/+7
| | | | | | | | | | | | | | ...yet! A lot of the current code should be shared for arm and thumb mode, but until we add tests and work out some of the details (e.g. checking the correct subtarget feature for G_SDIV) it's safer to bail out as early as possible for thumb targets. This should have arguably been part of r348347, which allowed Thumb functions to be handled by the IR Translator. llvm-svn: 348472
* [X86] Remove some leftover code for handling an i1 setcc type. NFCCraig Topper2018-12-061-5/+2
| | | | | | We should only need to handle i8 now. llvm-svn: 348460
* AArch64: Fix invalid CCMP emissionMatthias Braun2018-12-061-93/+124
| | | | | | | | | | | | | | | | | | The code emitting AND-subtrees used to check whether any of the operands was an OR in order to figure out if the result needs to be negated. However the OR could be hidden in further subtrees and not immediately visible. Change the code so that canEmitConjunction() determines whether the result of the generated subtree needs to be negated. Cleanup emission logic to use this. I also changed the code a bit to make all negation decisions early before we actually emit the subtrees. This fixes http://llvm.org/PR39550 Differential Revision: https://reviews.llvm.org/D54137 llvm-svn: 348444
* [Hexagon] Add intrinsics for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+30
| | | | llvm-svn: 348413
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-0516-500/+2763
| | | | llvm-svn: 348411
* [Hexagon] Foundation of support for Hexagon V66Krzysztof Parzyszek2018-12-0514-125/+226
| | | | llvm-svn: 348407
* [GISel]: Provide standard interface to observe changes in GISel passesAditya Nandakumar2018-12-057-8/+17
| | | | | | | | | | | | | https://reviews.llvm.org/D54980 This provides a standard API across GISel passes to observe and notify passes about changes (insertions/deletions/mutations) to MachineInstrs. This patch also removes the recordInsertion method in MachineIRBuilder and instead provides method to setObserver. Reviewed by: vkeles. llvm-svn: 348406
* [AArch64] Reword description of feature (NFC)Evandro Menezes2018-12-051-2/+2
| | | | | | | Reword the description of the feature that enables custom handling of cheap instructions. llvm-svn: 348398
* [SLH] Fix a nasty bug in SLH.Chandler Carruth2018-12-051-1/+3
| | | | | | | | | | | | | | | | | | | | Whenever we effectively take the address of a basic block we need to manually update that basic block to reflect that fact or later passes such as tail duplication and tail merging can break the invariants of the code. =/ Sadly, there doesn't appear to be any good way of automating this or even writing a reasonable assert to catch it early. The change seems trivially and obviously correct, but sadly the only really good test case I have is 1000s of basic blocks. I've tried directly writing a test case that happens to make tail duplication do something that crashes later on, but this appears to require an *amazingly* complex set of conditions that I've not yet reproduced. The change is technically covered by the tests because we mark the blocks as having their address taken, but that doesn't really count as properly testing the functionality. llvm-svn: 348374
* [AMDGPU]: Turn on the DPP combiner by defaultValery Pykhtin2018-12-051-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D55314 llvm-svn: 348371
* [X86][SSE] Begun adding modulo rotate support to LowerRotateSimon Pilgrim2018-12-051-4/+12
| | | | | | | | Prep work for PR38243 - mainly adding comments on where we need to add modulo support (doing so at the moment causes massive codegen regressions). I've also consistently added support for modulo folding for uniform constants (although at the moment we have no way to trigger this) and removed the old assertions. llvm-svn: 348366
* [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)Simon Pilgrim2018-12-052-11/+53
| | | | | | | | | | This is an initial patch to add a minimum level of support for funnel shifts to the SelectionDAG and to begin wiring it up to the X86 SHLD/SHRD instructions. Some partial legalization code has been added to handle the case for 'SlowSHLD' where we want to expand instead and I've added a few DAG combines so we don't get regressions from the existing DAG builder expansion code. Differential Revision: https://reviews.llvm.org/D54698 llvm-svn: 348353
* [ARM GlobalISel] Implement call lowering for Thumb2Diana Picus2018-12-051-13/+36
| | | | | | | | The only things that are different from arm are: * different opcodes for calls and returns * Thumb calls take predicate operands llvm-svn: 348347
* AArch64: support funclets in fastcall and swift_callSaleem Abdulrasool2018-12-051-0/+2
| | | | | | | | | | Functions annotated with `__fastcall` or `__attribute__((__fastcall__))` or `__attribute__((__swiftcall__))` may contain SEH handlers even on Win64. This matches the behaviour of cl which allows for `__try`/`__except` inside a `__fastcall` function. This was detected while trying to self-host clang on Windows ARM64. llvm-svn: 348337
* [AArch64][GlobalISel] Re-enable selection of volatile loads.Amara Emerson2018-12-051-6/+0
| | | | | | | | | | | | | | We previously disabled this in r323371 because of a bug where we selected an extending load, but didn't delete the old G_LOAD, resulting in two loads being generated for volatile loads. Since we now have dedicated G_SEXTLOAD/G_ZEXTLOAD operations, and that the tablegen patterns should no longer be able to select (ext(load x)) patterns, it should be safe to re-enable it. The old test case should still work as expected. llvm-svn: 348320
* AArch64: clean up some whitespace in Windows CC (NFC)Saleem Abdulrasool2018-12-041-1/+1
| | | | | | Drive by clean up for Windows ARM64 variadic CC (NFC). llvm-svn: 348310
* [AVR] Silence fallthrough warning. NFC.Nirav Dave2018-12-041-0/+1
| | | | llvm-svn: 348304
* [PowerPC] Make no-PIC default to match GCC - LLVMStefan Pintilie2018-12-041-3/+3
| | | | | | | | Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
* [SelectionDAG] Redefine isGAPlusOffset in terms of unwrapAddress. NFCI.Nirav Dave2018-12-042-18/+0
| | | | llvm-svn: 348288
* AMDGPU: Add f32 vectors to SGPR register classesMatt Arsenault2018-12-041-6/+6
| | | | llvm-svn: 348286
* [X86][SSE] Add SimplifyDemandedBitsForTargetNode handling for MOVMSKSimon Pilgrim2018-12-041-6/+39
| | | | | | Moves existing SimplifyDemandedBits call out of combineMOVMSK and add SimplifyDemandedVectorElts call based on the sign bits we need. llvm-svn: 348282
* [Hexagon] Remove unused checker functions from asm parserKrzysztof Parzyszek2018-12-041-2/+0
| | | | llvm-svn: 348269
* Fix MSVC "unknown pragma" warning. NFCI.Simon Pilgrim2018-12-041-0/+6
| | | | llvm-svn: 348256
* Fix -Wparentheses warning. NFCI.Simon Pilgrim2018-12-041-3/+2
| | | | llvm-svn: 348254
* [X86] Remove unnecessary peekThroughEXTRACT_SUBVECTORs call.Simon Pilgrim2018-12-041-2/+0
| | | | | | The GetSplatValue/IsSplatVector call will call this anyhow and the later code is just for a v2i64 type so doesn't need it. llvm-svn: 348253
* [TargetLowering] expandFP_TO_UINT - avoid FPE due to out of range conversion ↵Simon Pilgrim2018-12-042-0/+9
| | | | | | | | | | | | | | (PR17686) PR17686 demonstrates that for some targets FP exceptions can fire in cases where the FP_TO_UINT is expanded using a FP_TO_SINT instruction. The existing code converts both the inrange and outofrange cases using FP_TO_SINT and then selects the result, this patch changes this for 'strict' cases to pre-select the FP_TO_SINT input and the offset adjustment. The X87 cases don't need the strict flag but generates much nicer code with it.... Differential Revision: https://reviews.llvm.org/D53794 llvm-svn: 348251
* Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend featuresSimon Pilgrim2018-12-046-297/+72
| | | | | | | | | | | | | | | | | | | | | | | | | This patch splits backend features currently hidden behind architecture versions. For example, currently the only way to activate complex numbers extension is targeting an v8.3 architecture, where after the patch this extension can be added separately. This refactoring is required by the new command lines proposal: http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html Reviewers: DavidSpickett, olista01, t.p.northover Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio Differential revision: https://reviews.llvm.org/D54633 ........ This has been causing buildbots failures for the past 24 hours: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14386 llvm-svn: 348249
* [X86] Remove custom DAG combine for ↵Craig Topper2018-12-041-45/+0
| | | | | | | | SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG. We only needed this because it provided really aggressive constant folding even through constant pool entries created from build_vectors. The main case was for vXi8 MULH legalization which was happening as part of legalize DAG instead of as part of legalize vector ops. Now its part of vector op legalization and we've added special handling for build vectors of all constants there. This has removed the need for this code on the list tests we have. llvm-svn: 348237
* [ARM64][Windows] Fix local stack size for funcletsSanjin Sijaric2018-12-041-3/+8
| | | | | | | | | | | The comment was misplaced, and the code didn't do what the comment indicated, namely ignoring the varargs portion when computing the local stack size of a funclet in emitEpilogue. This results in incorrect offset computations within funclets that are contained in vararg functions. Differential Revision: https://reviews.llvm.org/D55096 llvm-svn: 348222
* [MachineOutliner] Move stack instr check logic to getOutliningCandidateInfoJessica Paquette2018-12-041-96/+72
| | | | | | | | | | | | | | | | This moves the stack check logic into a lambda within getOutliningCandidateInfo. This allows us to be less conservative with stack checks. Whether or not a stack instruction is safe to outline is dependent on the frame variant and call variant of the outlined function; only in cases where we modify the stack can these be unsafe. So, if we move that logic later, when we're looking at an individual candidate, we can make better decisions here. This gives some code size savings as a result. llvm-svn: 348220
* [MachineOutliner][AArch64][NFC] Add early exit to candidate discarding logicJessica Paquette2018-12-041-0/+6
| | | | | | | | If we dropped too many candidates to be beneficial when dropping candidates that modify the stack, there's no reason to check for other cost model qualities. llvm-svn: 348219
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-033-1233/+3613
| | | | llvm-svn: 348206
* [Hexagon] Extract operand decoders into a separate file, NFCKrzysztof Parzyszek2018-12-032-56/+74
| | | | | | | These decoders are automatically generated. Keeping them separated makes updating architectures easier. llvm-svn: 348196
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