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* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-139-30/+41
| | | | llvm-svn: 163803
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-132-0/+9
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-133-1/+39
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Misc.Akira Hatanaka2012-09-121-3/+6
| | | | | | | | | 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. llvm-svn: 163753
* Fix PR11985Michael Liao2012-09-127-25/+36
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* [ms-inline asm] Make the operand size directives case insensitive.Chad Rosier2012-09-121-8/+9
| | | | llvm-svn: 163729
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-1/+1
| | | | llvm-svn: 163721
* Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky2012-09-121-2/+1
| | | | | | was fixed in r163713. llvm-svn: 163715
* This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky2012-09-124-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! llvm-svn: 163713
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
| | | | llvm-svn: 163710
* Indentation fixes. No functional change.Craig Topper2012-09-121-8/+8
| | | | llvm-svn: 163682
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Release build: guard dump functions withManman Ren2012-09-112-2/+2
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* StringSwitchify.Chad Rosier2012-09-111-8/+10
| | | | llvm-svn: 163649
* Simplify logic. No functional change intended.Chad Rosier2012-09-111-9/+8
| | | | llvm-svn: 163648
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+4
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Make a bunch of lowering helper functions static instead of member ↵Craig Topper2012-09-112-82/+56
| | | | | | functions. No functional change. llvm-svn: 163596
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-112-2/+2
| | | | | | table size. llvm-svn: 163594
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-112-510/+18
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-107-14/+14
| | | | llvm-svn: 163561
* Revert r163556. Missed updates to tablegen files.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163557
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-102-4/+4
| | | | llvm-svn: 163556
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-103-3/+3
| | | | llvm-svn: 163547
* [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier2012-09-102-4/+6
| | | | | | and update the printOperand() function accordingly. llvm-svn: 163544
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-103-7/+15
| | | | | | - Fix an remaining issue of PR11674 as well llvm-svn: 163528
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Add boolean simplification support from CMOVMichael Liao2012-09-101-12/+42
| | | | | | | | - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. llvm-svn: 163516
* The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky2012-09-101-4/+15
| | | | | | | | undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. llvm-svn: 163506
* Make helper function static.Benjamin Kramer2012-09-101-2/+1
| | | | llvm-svn: 163504
* Add missing space before {. No functionality change.Nick Lewycky2012-09-091-1/+1
| | | | llvm-svn: 163484
* Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper2012-09-082-20/+41
| | | | llvm-svn: 163473
* Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper2012-09-081-2/+3
| | | | llvm-svn: 163463
* Add support for lowering FABS of vector types.Craig Topper2012-09-081-12/+25
| | | | llvm-svn: 163461
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-082-0/+2
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-071-1/+1
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-073-3/+1
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-5/+6
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.Benjamin Kramer2012-09-071-8/+8
| | | | llvm-svn: 163383
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-071-0/+20
| | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
* The Mips standalone assembler intial directive support.Jack Carter2012-09-071-0/+43
| | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-072-7/+220
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
* Remove unused variable introduced by r163346.David Blaikie2012-09-061-2/+0
| | | | llvm-svn: 163359
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-061-7/+211
| | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic llvm-svn: 163346
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-062-0/+4
| | | | | | No functional change. llvm-svn: 163339
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-2/+2
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
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