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* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-313-36/+76
| | | | llvm-svn: 162999
* Clean up AddedComplexity further after adding UseSSExMichael Liao2012-08-311-17/+13
| | | | llvm-svn: 162973
* Fix a couple of typos in EmitAtomic.Jakob Stoklund Olesen2012-08-311-2/+2
| | | | | | | | | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-311-1/+1
| | | | | | | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v' prefix, resulting in mis-assembly of the vanilla movd instruction. llvm-svn: 162963
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-311-64/+42
| | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961
* Fix for r162954. Return the Error.Chad Rosier2012-08-301-2/+2
| | | | llvm-svn: 162955
* Move a check to the validateInstruction() function where it more properly ↵Chad Rosier2012-08-301-11/+13
| | | | | | belongs. llvm-svn: 162954
* Typo.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162952
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-305-122/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. llvm-svn: 162919
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
| | | | | | | | [Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. llvm-svn: 162916
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162915
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-301-2/+71
| | | | llvm-svn: 162898
* Only perform DAG combine on FMAs of legal types.Craig Topper2012-08-301-0/+4
| | | | llvm-svn: 162892
* Fix PR13727Michael Liao2012-08-301-3/+7
| | | | | | | | | | | - The root cause is that target constant materialization in X86 fast-isel creates a PC-rel addressing which may overflow 32-bit range in non-Small code model if .rodata section is allocated too far away from code segment in MCJIT, which uses Large code model so far. - Follow the similar logic to fix non-Small code model in fast-isel by skipping non-Small code model. llvm-svn: 162881
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-291-2/+2
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Reserve space for the mandatory traceback fields on PPC64.Hal Finkel2012-08-291-4/+8
| | | | | | | | | | | | | | | | | | | | | We need to reserve space for the mandatory traceback fields, though leaving them as zero is appropriate for now. Although the ABI calls for these fields to be filled in fully, no compiler on Linux currently does this, and GDB does not read these fields. GDB uses the first word of zeroes during exception handling to find the end of the function and the size field, allowing it to compute the beginning of the function. DWARF information is used for everything else. We need the extra 8 bytes of pad so the size field is found in the right place. As a comparison, GCC fills in a few of the fields -- language, number of saved registers -- but ignores the rest. IBM's proprietary OSes do make use of the full traceback table facility. Patch by Bill Schmidt. llvm-svn: 162854
* Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover2012-08-291-45/+53
| | | | llvm-svn: 162844
* Make helper function static.Benjamin Kramer2012-08-291-1/+1
| | | | llvm-svn: 162843
* Make MemoryBuiltins aware of TargetLibraryInfo.Benjamin Kramer2012-08-291-1/+20
| | | | | | | | | | | | | | | | This disables malloc-specific optimization when -fno-builtin (or -ffreestanding) is specified. This has been a problem for a long time but became more severe with the recent memory builtin improvements. Since the memory builtin functions are used everywhere, this required passing TLI in many places. This means that functions that now have an optional TLI argument, like RecursivelyDeleteTriviallyDeadFunctions, won't remove dead mallocs anymore if the TLI argument is missing. I've updated most passes to do the right thing. Fixes PR13694 and probably others. llvm-svn: 162841
* Convert FMA4 patterns to use target specific nodes instead of intrinsics to ↵Craig Topper2012-08-293-38/+36
| | | | | | align with FMA3. llvm-svn: 162829
* Cleanup sloppy code. Jakob's review.Andrew Trick2012-08-291-4/+3
| | | | llvm-svn: 162825
* [arm-fast-isel] Add support for ARM PIC.Jush Lu2012-08-291-6/+16
| | | | llvm-svn: 162823
* Fix ARM vector copies of overlapping register tuples.Andrew Trick2012-08-291-0/+13
| | | | | | | | I have tested the fix, but have not been successfull in generating a robust unit test. This can only be exposed through particular register assignments. llvm-svn: 162821
* cleanupAndrew Trick2012-08-291-21/+19
| | | | llvm-svn: 162820
* Typo.Chad Rosier2012-08-281-1/+1
| | | | llvm-svn: 162807
* Add comments on the literal value used.Michael Liao2012-08-281-1/+1
| | | | llvm-svn: 162805
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-284-3/+54
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
* Explicitly update the number of nodes to be traversedMichael Liao2012-08-281-1/+1
| | | | llvm-svn: 162780
* Some instructions are passed to the assembler to beJack Carter2012-08-281-20/+24
| | | | | | | | | | | | | transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. llvm-svn: 162779
* Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky2012-08-281-0/+15
| | | | | | | | | | traceback table on PowerPC64. This helps gdb handle exceptions. The other mandatory fields are ignored by gdb and harder to implement so just add there a FIXME. Patch by Bill Schmidt. PR13641. llvm-svn: 162778
* Follow-up patch to r162731.Akira Hatanaka2012-08-281-8/+9
| | | | | | | | Fix a couple of bugs in mips' long branch pass. This patch was supposed to be committed along with r162731, so I don't have a new test case. llvm-svn: 162777
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-288-2/+609
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-281-1/+1
| | | | | | | | it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> llvm-svn: 162741
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-283-18/+10
| | | | llvm-svn: 162740
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-283-31/+18
| | | | llvm-svn: 162738
* Fix PR12312Michael Liao2012-08-281-10/+112
| | | | | | | | | | - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-286-169/+43
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Fix mips' long branch pass.Akira Hatanaka2012-08-281-105/+128
| | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. llvm-svn: 162731
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Allow remat of LI on PPC.Hal Finkel2012-08-282-1/+3
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-283-8/+34
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+9
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen2012-08-281-3/+3
| | | | llvm-svn: 162714
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-276-43/+169
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-271-2/+3
| | | | | | <rdar://problem/12183003> llvm-svn: 162703
* Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper2012-08-271-56/+0
| | | | | | SelectionDAGBuilder. llvm-svn: 162661
* Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper2012-08-271-13/+9
| | | | | | unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. llvm-svn: 162658
* Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper2012-08-271-4/+4
| | | | | | removing the need for an explicit 'neverHasSideEffects = 1' llvm-svn: 162656
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-272-48/+62
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-248-25/+22
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
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