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* Fix compilation for some targets other than x86.Argyrios Kyrtzidis2009-04-302-2/+0
| | | | llvm-svn: 70522
* Make DebugLoc independent of DwarfWriter.Argyrios Kyrtzidis2009-04-302-0/+2
| | | | | | | | -Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable* -Remove DwarfWriter::getOrCreateSourceID -Make necessary changes for the above (fix callsites, etc.) llvm-svn: 70520
* getCommonSubClass() - Calculate the largest common sub-class of two registerJakob Stoklund Olesen2009-04-301-0/+42
| | | | | | | | | classes. This is implemented as a function rather than a method on TargetRegisterClass because it is symmetric in its arguments. llvm-svn: 70512
* Set mayLoad on MOVZX32_NOREXrm8 too.Dan Gohman2009-04-301-0/+1
| | | | llvm-svn: 70466
* Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.Evan Cheng2009-04-301-1/+3
| | | | llvm-svn: 70461
* remove progname which is never set. PR4085Chris Lattner2009-04-301-2/+1
| | | | llvm-svn: 70453
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-2949-132/+216
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Fix infinite recursion in the C++ code which handles movddup by making it ↵Nate Begeman2009-04-292-46/+13
| | | | | | unnecessary. llvm-svn: 70425
* Implement review feedback for vector shuffle work.Nate Begeman2009-04-292-31/+34
| | | | llvm-svn: 70372
* Add a public method called getAddressSpace() to the GlobalAddressSDNode.Sanjiv Gupta2009-04-291-2/+1
| | | | llvm-svn: 70366
* Second attempt:Bill Wendling2009-04-2949-191/+227
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* Properly print 'P' modifier on inline asm memory operands.Anton Korobeynikov2009-04-282-8/+9
| | | | | | | This should fix PR3379 and PR4064. Patch inspired by Edwin Török! llvm-svn: 70328
* GlobalValue is always pointer type, so an assert isn't required.Sanjiv Gupta2009-04-281-6/+1
| | | | llvm-svn: 70300
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-2849-227/+191
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-2849-191/+227
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-279-1641/+1208
| | | | | | | | | | | | | | PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. llvm-svn: 70225
* Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use theseDan Gohman2009-04-273-32/+71
| | | | | | | | | | | to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
* Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman2009-04-275-42/+42
| | | | | | GR32_ABCD, and GR64_ABCD, respectively, to help describe them. llvm-svn: 70210
* Break up long multi-mnemonic strings into separate lines for readability.Dan Gohman2009-04-272-12/+27
| | | | llvm-svn: 70209
* Revised 68749 to allow matching of load/stores for address spaces < 256.Mon P Wang2009-04-271-9/+9
| | | | llvm-svn: 70197
* add support for detecting process features on win64, patch byChris Lattner2009-04-251-36/+50
| | | | | | Nicolas Capens! llvm-svn: 70057
* Change LowerCallResult method so that CCValAssign::BCvt can be used withBob Wilson2009-04-251-16/+16
| | | | | | f64 types. This is not used for anything yet. llvm-svn: 70006
* Adjust a comment to reflect what the code does. Splitting a 64-bit argumentBob Wilson2009-04-241-1/+1
| | | | | | | between registers and the stack may be required with the APCS ABI, but it isn't tied to using a particular version of the ARM architecture. llvm-svn: 69978
* Fix up some problems with getCopyToReg and getCopyFromReg nodes beingBob Wilson2009-04-241-8/+12
| | | | | | | | | chained and "flagged" together. I also made a few changes to handle the chain and flag values more consistently. I found these problems by inspection so I'm not aware of anything that breaks because of them (thus no testcase). llvm-svn: 69977
* Remove unnecessary references to f32 types. After specifying that f32Bob Wilson2009-04-241-4/+4
| | | | | | | should be bit-converted to i32, it is sufficient to list only i32 in subsequent definitions. llvm-svn: 69973
* Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is notRafael Espindola2009-04-243-37/+26
| | | | | | very elegant, but neither is the tls specification :-( llvm-svn: 69968
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-249-1195/+1633
| | | | llvm-svn: 69967
* PR2957Nate Begeman2009-04-249-1633/+1195
| | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. llvm-svn: 69952
* Fix spurious indentation in a comment.Dan Gohman2009-04-231-1/+1
| | | | llvm-svn: 69934
* Banksel immediate constant will always immediately follow the GA/ES, so scan ↵Sanjiv Gupta2009-04-231-18/+20
| | | | | | an insn from beginnin to find out the banksel operand. llvm-svn: 69883
* Add support for printing MO_ExternalSymbol operands inDan Gohman2009-04-231-2/+4
| | | | | | | memory operand tuples. This doesn't ever come up in normal code however. llvm-svn: 69848
* Make the function begin label start after ther data pointer.Sanjiv Gupta2009-04-223-9/+12
| | | | | | The address of data frame for function can be obtained by subtracting 2 from the function begin label. llvm-svn: 69801
* Get rid of what looks like a copy-and-pasted typo.Duncan Sands2009-04-211-3/+3
| | | | | | Spotted by gcc-4.5. llvm-svn: 69673
* TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.Rafael Espindola2009-04-212-2/+2
| | | | | | This fixes PR4002. llvm-svn: 69672
* Handle direct aggregate type arguments.Sanjiv Gupta2009-04-212-51/+36
| | | | llvm-svn: 69665
* Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman2009-04-201-20/+29
| | | | | | | This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. llvm-svn: 69635
* Remove unused variable.Daniel Dunbar2009-04-201-1/+0
| | | | llvm-svn: 69624
* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-202-30/+8
| | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. llvm-svn: 69615
* Match C backend only if it explicitly requested.Devang Patel2009-04-201-2/+3
| | | | llvm-svn: 69613
* Emit the auto variables of a function into a different section than parameters.Sanjiv Gupta2009-04-202-24/+46
| | | | llvm-svn: 69605
* Fixed a few 64 bit cases in X86InstrInfo::commuteInstructionMon P Wang2009-04-181-3/+3
| | | | llvm-svn: 69417
* Recommit r69335 and r69336. These were not causing problems.Bill Wendling2009-04-171-3/+5
| | | | llvm-svn: 69394
* Move the AddLiveIn function definition closer to its uses.Bob Wilson2009-04-171-11/+11
| | | | llvm-svn: 69382
* Rearrange code to reduce indentation.Bob Wilson2009-04-171-41/+38
| | | | llvm-svn: 69381
* Clean up formatting, remove trailing whitespace, fix comment typos andBob Wilson2009-04-173-44/+31
| | | | | | punctuation. No functional changes. llvm-svn: 69378
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-176-305/+561
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* For general dynamic TLS access we must useRafael Espindola2009-04-173-36/+32
| | | | | | | | | leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. llvm-svn: 69350
* Revert r69335 and r69336. They were causing build failures.Bill Wendling2009-04-171-5/+3
| | | | llvm-svn: 69347
* MOV8rr_NOREX is a "Move" instruction. This doesn't currentlyDan Gohman2009-04-171-0/+1
| | | | | | | matter, because this instruction isn't generated until after things that care. llvm-svn: 69336
* Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything atDan Gohman2009-04-171-3/+4
| | | | | | present, but it's inconsistent. llvm-svn: 69335
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