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* [ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2014-05-152-10/+25
| | | | llvm-svn: 208860
* [mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders2014-05-157-4/+93
| | | | | | | | | | | | | | | | Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
* [mips][mips64r6] Add aui, daui, dahi, and datiDaniel Sanders2014-05-153-5/+59
| | | | | | | | | | | | Summary: Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3759 llvm-svn: 208857
* [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.Daniel Sanders2014-05-151-2/+0
| | | | | | | | | | | | | | | Summary: They aren't implemented for any ISA at the moment. Depends on D3670 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3671 llvm-svn: 208855
* Fix some dyslexia in an assert messageJonathan Roelofs2014-05-151-2/+2
| | | | llvm-svn: 208842
* Fix typosAlp Toker2014-05-152-3/+3
| | | | llvm-svn: 208839
* [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out ↵Jiangning Liu2014-05-155-101/+377
| | | | | | argument stack from callee. llvm-svn: 208837
* Move the TargetMachine MC options to MCTargetOptions. No functionalEric Christopher2014-05-151-4/+0
| | | | | | change. llvm-svn: 208832
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-1420-106/+106
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* ARM-BE: test files for vector argument passingChristian Pirker2014-05-141-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D3766 llvm-svn: 208793
* [ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2014-05-141-0/+17
| | | | | | Reviewed at http://reviews.llvm.org/D3741 llvm-svn: 208792
* X86: If we have an instruction that sets a flag and a zero test on the input ↵Benjamin Kramer2014-05-141-3/+63
| | | | | | | | | | | | | | | | | | | | | of that instruction try to eliminate the test. For example tzcntl %edi, %ebx testl %edi, %edi je .label can be rewritten into tzcntl %edi, %ebx jb .label A minor complication is that tzcnt sets CF instead of ZF when the input is zero, we have to rewrite users of the flags from ZF to CF. Currently we recognize patterns using lzcnt, tzcnt and popcnt. Differential Revision: http://reviews.llvm.org/D3454 llvm-svn: 208788
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-142-4/+52
| | | | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208784
* ARM64: remove unneeded InstPrinter hacksTim Northover2014-05-141-32/+0
| | | | | | | Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. llvm-svn: 208781
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-144-2/+37
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* Fix typo in function name.Eric Christopher2014-05-141-5/+5
| | | | llvm-svn: 208743
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* Save the optimization level the subtarget was created with in aEric Christopher2014-05-132-15/+14
| | | | | | | | | | member variable and sink the initialization of crbits into the subtarget feature reset code. No functional change, but this refactor will be used in a future commit. llvm-svn: 208726
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-131-4/+14
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-131-14/+4
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-137-21/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-131-4/+14
| | | | llvm-svn: 208689
* [mips] Free up two values in SubtargetFeatureFlag by folding the redundant ↵Daniel Sanders2014-05-132-6/+5
| | | | | | | | | | | | | | | | | | | | | IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 llvm-svn: 208685
* [un]wrap extracted from lib/Target/Target[MachineC].cpp, ↵Artyom Skrobov2014-05-132-25/+0
| | | | | | lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h llvm-svn: 208680
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-132-11/+8
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-131-3/+11
| | | | | | | | | | | Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. llvm-svn: 208660
* Try to fix an SDAG dependence issue with sretReid Kleckner2014-05-122-18/+23
| | | | | | | | | | | | | | | | r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
* Use cast<> for unchecked useMatt Arsenault2014-05-121-1/+1
| | | | llvm-svn: 208627
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-122-0/+17
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* Use cast<> for unchecked useMatt Arsenault2014-05-121-2/+2
| | | | llvm-svn: 208618
* Use range forMatt Arsenault2014-05-122-6/+4
| | | | llvm-svn: 208617
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-1212-41/+86
| | | | llvm-svn: 208607
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-122-72/+67
| | | | llvm-svn: 208606
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-123-58/+94
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-123-4/+10
| | | | llvm-svn: 208604
* Revert: r208582 - [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-122-52/+4
| | | | | | Accidentally committed an unreviewed patch. Reverted it. llvm-svn: 208583
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-122-4/+52
| | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: jkolek, vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208582
* [mips][mips64r6] Add d?div, d?mod, d?divu, d?moduDaniel Sanders2014-05-122-8/+32
| | | | | | | | | | | | Summary: Depends on D3668 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3669 llvm-svn: 208579
* [mips][mips64r6] Added mul/mulu/muh/muhuDaniel Sanders2014-05-125-9/+115
| | | | | | | | | | | | Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
* Silencing an MSVC warning about not all control paths returning a value ↵Aaron Ballman2014-05-121-0/+1
| | | | | | (even though the switch is fully covered). No functional change. llvm-svn: 208565
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-121-198/+0
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. llvm-svn: 208564
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-126-330/+241
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* Remove an always true argument.Rafael Espindola2014-05-121-1/+1
| | | | llvm-svn: 208557
* X86: Make sure that we have SSE4.1 before we generate insertps nodes.Benjamin Kramer2014-05-121-1/+1
| | | | | | PR19721. llvm-svn: 208552
* [mips] Marked up instructions added in MIPS32 and tested that IAS for ↵Daniel Sanders2014-05-121-8/+8
| | | | | | | | | | | | | | | | -mcpu=mips2 does not accept them Summary: To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are explicitly tested. Depends on D3695 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3696 llvm-svn: 208549
* Remove MCUseCFI from TargetMachine.Rafael Espindola2014-05-121-1/+0
| | | | | | It was always true. llvm-svn: 208547
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-126-9/+23
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64Daniel Sanders2014-05-127-25/+17
| | | | | | | | | | | | | | | | | | | | | Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
* [mips] Fold FeatureSEInReg into FeatureMips32r2Daniel Sanders2014-05-127-26/+20
| | | | | | | | | | | | Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-127-23/+14
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
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