summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* AArch64: Follow-up to r212073Duncan P. N. Exon Smith2014-07-011-4/+4
| | | | | | | | In r212073 I missed a call of `use_begin()` that assumed the wrong semantics. It's not clear to me at all what this code does without the fix, so I'm not sure how to write a testcase. llvm-svn: 212075
* AArch64: Actually do address type promotionDuncan P. N. Exon Smith2014-06-301-3/+3
| | | | | | | | AArch64AddressTypePromotion was doing nothing because it was using the old semantics of `Use` and `uses()`, when it really wanted to get at the `users()`. llvm-svn: 212073
* Fix 'platform-specific' hyphenationsAlp Toker2014-06-302-3/+3
| | | | llvm-svn: 212056
* R600: Move mul combine to separate functionMatt Arsenault2014-06-302-28/+35
| | | | llvm-svn: 212052
* R600: Remove unused declarations leftover from AMDILMatt Arsenault2014-06-301-8/+0
| | | | llvm-svn: 212051
* [X86] Add support for builtin to read performance monitoring counters.Andrea Di Biagio2014-06-304-2/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a new builtin instruction called __builtin_ia32_rdpmc. Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can be used to read performance monitoring counters. It takes as input the index of the performance counter to read, and returns the value of the specified performance counter as a 64-bit number. Calls to this new builtin will map to instruction RDPMC. The index in input to the builtin call is moved to register %ECX. The result of the builtin call is the value of the specified performance counter (RDPMC would return that quantity in registers RDX:RAX). This patch: - Adds builtin int_x86_rdpmc as a GCCBuiltin; - Adds a new x86 DAG node called 'RDPMC_DAG'; - Teaches how to lower this new builtin; - Adds an ISel pattern to select instruction RDPMC; - Fixes the definition of instruction RDPMC adding %RAX and %RDX as implicit definitions, and adding %ECX as implicit use; - Adds a LLVM test to verify that the new builtin is correctly selected. llvm-svn: 212049
* [AArch64] Unsized types don't specify an alignment.Chad Rosier2014-06-301-2/+3
| | | | | | PR20109 llvm-svn: 212045
* [AArch64] Convert mul x, -(pow2 +/- 1) to shift + add/sub.Chad Rosier2014-06-301-17/+39
| | | | | | | The combine for mul x, pow2 +/- 1 is unchanged. Test cases for both combines as well as mul x, pow2 have been added as well. llvm-svn: 212044
* ARM: take care not to set the ThumbFunc bit on TLS data symbolsScott Douglass2014-06-301-1/+2
| | | | | | | | This fixes LNT SingleSource/UnitTests/Threads with -mthumb. Differential Revision: http://reviews.llvm.org/D4324 llvm-svn: 212029
* X86: fix commentSaleem Abdulrasool2014-06-301-1/+1
| | | | | | Fix a comment typo `DbgLocLImport` instead of `DLLImport`. llvm-svn: 212012
* ARM: use symbolic name for constantSaleem Abdulrasool2014-06-301-1/+1
| | | | | | | This just changes the constant value to the symbolic name corresponding to it. NFC. llvm-svn: 212011
* CodeGen: rename Win64 ExceptionHandling to WinEHSaleem Abdulrasool2014-06-292-10/+10
| | | | | | | | | | This exception format is not specific to Windows x64. A similar approach is taken on nearly all architectures. Generalise the name to reflect reality. This will eventually be used for Windows on ARM data emission as well. Switch the enum and namespace into an enum class. llvm-svn: 212000
* MC: rename EmitWin64EH routinesSaleem Abdulrasool2014-06-292-15/+13
| | | | | | | | | | | | | | | Rename the routines to reflect the reality that they are more related to call frame information than to Win64 EH. Although EH is implemented in an intertwined manner by augmenting with an exception handler and an associated parameter, the majority of these routines emit information required to unwind the frames. This also helps identify that these routines are generic for most windows platforms (they apply equally to nearly all architectures except x86) although the encoding of the information is architecture dependent. Unwinding data is emitted via EmitWinCFI* and exception handling information via EmitWinEH*. llvm-svn: 211994
* Add ops() method to SDNode that returns an ArrayRef<SDUse>. Use it to ↵Craig Topper2014-06-292-11/+8
| | | | | | simplify some code. llvm-svn: 211993
* [x86] Fix a bug in the v8i16 shuffling exposed by the new splat-likeChandler Carruth2014-06-281-1/+1
| | | | | | | | | | | lowering for v16i8. ASan and some bots caught this bug with existing test cases. Fixing it even fixed a miscompile with one of the test cases. I'm still a bit suspicious of this test case as I've not taken a proper amount of time to think about it, but the fix here is strict goodness. llvm-svn: 211976
* [x86] Add handling for splat-like widenings of v16i8 shuffles.Chandler Carruth2014-06-281-0/+80
| | | | | | | | | | | | | | | | These show up really frequently, not the least with actual splats. =] We lowered these quite badly before. The new code path tries to widen i8 shuffles to i16 shuffles in a splat-like way. There are still some inefficiencies in our i16 splat logic though, so we aren't really done here. Also, for certain patterns (bit of a gather-and-splat) we still generate pretty silly code, and I've left a fixme for addressing it. However, I'm not actually worried about this code pattern as much. The old shuffle lowering generates a 29 instruction monstrosity for it that should execute much more slowly. llvm-svn: 211974
* [x86] Fix another bug hit when bootstrapping with the new shuffleChandler Carruth2014-06-271-1/+1
| | | | | | | | | | | | | lowering. For maximum irony, I had already discovered this bug, diagnosed it, and left FIXMEs about it in the test cases. =[ I just failed to go back over those until after i had reduced a bootstrap miscompile down to a single TU, stared at the assembly for an hour, and figured out the bug. Again. Oh well. llvm-svn: 211955
* [NVPTX] Use GreatestCommonDivisor64 from MathExtras instead of using our ↵Justin Holewinski2014-06-271-14/+4
| | | | | | own. Thanks Hal! llvm-svn: 211952
* [NVPTX] Add reflect intrinsic (better than matching by function name)Justin Holewinski2014-06-271-22/+47
| | | | | | Also clean up some of the logic in NVVMReflect.cpp while we're messing around in there. llvm-svn: 211948
* [NVPTX] Handle all possible vector types in getSetCCResultType, not just the ↵Justin Holewinski2014-06-271-2/+2
| | | | | | ones representable as MVTs llvm-svn: 211947
* [NVPTX] Add 'b' asm constraintJustin Holewinski2014-06-271-0/+3
| | | | llvm-svn: 211946
* [NVPTX] Simplify some argument lowering logicJustin Holewinski2014-06-271-13/+8
| | | | llvm-svn: 211945
* [NVPTX] Do not process samplers in GenericToNVVMJustin Holewinski2014-06-271-1/+1
| | | | llvm-svn: 211944
* [NVPTX] Error out if initializer is given for variable in an address space ↵Justin Holewinski2014-06-271-7/+18
| | | | | | that does not support initialization llvm-svn: 211943
* [NVPTX] Add support for .managed variables for UVMJustin Holewinski2014-06-271-0/+5
| | | | llvm-svn: 211942
* [NVPTX] Emit .weak linkage for link_once, weak, available_externally, and ↵Justin Holewinski2014-06-271-0/+4
| | | | | | common linkage llvm-svn: 211941
* [NVPTX] Variables that start with llvm. or nvvm. are reserved and should not ↵Justin Holewinski2014-06-271-0/+5
| | | | | | be emitted llvm-svn: 211940
* [NVPTX] Fix handling of ldg/ldu intrinsics.Justin Holewinski2014-06-274-100/+375
| | | | | | | | | | The address space of the pointer must be global (1) for these intrinsics. There must also be alignment metadata attached to the intrinsic calls, e.g. %val = tail call i32 @llvm.nvvm.ldu.i.global.i32.p1i32(i32 addrspace(1)* %ptr), !align !0 !0 = metadata !{i32 4} llvm-svn: 211939
* [NVPTX] Clean up argument lowering code and properly handle alignment for ↵Justin Holewinski2014-06-271-90/+76
| | | | | | structs and vectors llvm-svn: 211938
* [NVPTX] Add missing boolean vector contents flagJustin Holewinski2014-06-271-0/+1
| | | | llvm-svn: 211937
* [NVPTX] Add support for [SHL,SRA,SRL]_PARTSJustin Holewinski2014-06-273-0/+170
| | | | llvm-svn: 211936
* [NVPTX] Implement fma and imad contraction as target DAGCombiner patternsJustin Holewinski2014-06-274-126/+549
| | | | | | This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer llvm-svn: 211935
* [NVPTX] Add support for efficient rotate instructions on SM 3.2+Justin Holewinski2014-06-272-4/+170
| | | | llvm-svn: 211934
* [NVPTX] Add missing isel patterns for 64-bit atomicsJustin Holewinski2014-06-271-0/+98
| | | | llvm-svn: 211933
* [NVPTX] Add isel patterns for bit-field extract (bfe)Justin Holewinski2014-06-273-0/+238
| | | | llvm-svn: 211932
* [NVPTX] Add support for isspacep instructionJustin Holewinski2014-06-272-0/+40
| | | | llvm-svn: 211931
* [NVPTX] Add support for envreg readsJustin Holewinski2014-06-272-1/+45
| | | | llvm-svn: 211930
* [NVPTX] Add target options for PTX 3.2/4.0 and SM 5.0 (Maxwell)Justin Holewinski2014-06-272-7/+11
| | | | | | Default PTX version is set to PTX 3.2 llvm-svn: 211929
* [NVPTX] Update sub-target feature detectionJustin Holewinski2014-06-271-3/+5
| | | | llvm-svn: 211928
* [NVPTX] Directly control the Machine SSA passes that are invoked for NVPTX.Justin Holewinski2014-06-271-0/+41
| | | | | | | NVPTX is a bit special in the optimizations it requires, so this gives us better control over the backend optimization pipeline. llvm-svn: 211927
* [NVPTX] Emit .weak when linkage is not external, internal, or privateJustin Holewinski2014-06-271-0/+7
| | | | llvm-svn: 211926
* [NVPTX] Just use getTypeAllocSize() when computing return value size for ↵Justin Holewinski2014-06-271-17/+1
| | | | | | structures and vectors llvm-svn: 211925
* [x86] Fix a miscompile in the new shuffle lowering uncovered byChandler Carruth2014-06-271-13/+13
| | | | | | | | | a bootstrap. I managed to mis-remember how PACKUS worked on x86, and was using undef for the high bytes instead of zero. The fix is fairly obvious. llvm-svn: 211922
* R600: Move trivial getters into header, use initializer listMatt Arsenault2014-06-272-95/+82
| | | | llvm-svn: 211917
* [FastISel][X86] Fix typos.Juergen Ributzka2014-06-271-13/+13
| | | | llvm-svn: 211911
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-271-2/+24
| | | | llvm-svn: 211906
* Clean up unused variable warning in release build.Alexander Kornienko2014-06-271-0/+1
| | | | llvm-svn: 211902
* [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndexUlrich Weigand2014-06-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | I've run into a bug where current LLVM at -O0 (with fast-isel) generated invalid code like: ld 0, 20936(1) # 8-byte Folded Reload stw 12, 10348(0) stw 12, 10344(0) The underlying vreg had been introduced as base register by the Local Stack Slot Allocation pass. That register was constrained to G8RC by PPCRegisterInfo::materializeFrameBaseRegister to match the ADDI instruction used to set it, but it was *not* constrained to G8RC_NOX0 to fit the *use* of the register in an address. That should have happened in PPCRegisterInfo::resolveFrameIndex. This patch adds an appropriate constrainRegClass call. Reviewed by Hal Finkel. llvm-svn: 211897
* [x86] Clean up some unused variables, especially in release builds.Chandler Carruth2014-06-271-9/+6
| | | | llvm-svn: 211894
* [x86] Teach the target combine step to aggressively fold pshufd insturcions.Chandler Carruth2014-06-271-11/+77
| | | | | | | | | | | | | Summary: This allows it to fold pshufd instructions across intervening half-shuffles and other noise. This pattern actually shows up in the generic lowering tests, but I've also added direct tests using intrinsics to make sure that the specific desired functionality is working even if the lowering stuff changes in the future. Differential Revision: http://reviews.llvm.org/D4292 llvm-svn: 211892
OpenPOWER on IntegriCloud