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* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-0915-24/+38
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11037 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241776
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-0954-815/+928
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11028 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241775
* Make TargetTransformInfo keeping a reference to the Module DataLayoutMehdi Amini2015-07-0914-125/+37
| | | | | | | | | | | | | | | | | | | | DataLayout is no longer optional. It was initialized with or without a DataLayout, and the DataLayout when supplied could have been the one from the TargetMachine. Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11021 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241774
* Redirect DataLayout from TargetMachine to Module in ComputeValueVTs()Mehdi Amini2015-07-097-48/+50
| | | | | | | | | | | | | | | | | | | | Summary: Avoid using the TargetMachine owned DataLayout and use the Module owned one instead. This requires passing the DataLayout up the stack to ComputeValueVTs(). This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11019 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241773
* [x86] enable machine combiner reassociations for scalar single-precision ↵Sanjay Patel2015-07-081-2/+4
| | | | | | multiplies llvm-svn: 241752
* Add missing dependency to Hexagon target.Diego Novillo2015-07-081-0/+1
| | | | | | | A recent patch added calls to isInstructionTriviallyDead without the corresponding dependency on TransformUtils. llvm-svn: 241731
* [Win64] Only treat some functions as having the Win64 conventionReid Kleckner2015-07-081-2/+20
| | | | | | | | | | | | | | | | All the usual X86 target-specific conventions are collapsed to the normal Win64 convention, but the custom conventions like GHC and webkit should not be. Previously we would assume that the caller allocated 32 bytes of shadow space for us, which is not how webkit_jscc or other custom conventions are supposed to work. Based on a patch by peavo@outlook.com. Fixes PR24051. llvm-svn: 241725
* [Hexagon] Implement commoning of GetElementPtr instructionsKrzysztof Parzyszek2015-07-083-0/+1340
| | | | llvm-svn: 241714
* [SEH] Ensure that empty __except blocks have their own BBReid Kleckner2015-07-081-0/+5
| | | | | | | | | The 32-bit lowering assumed that WinEHPrepare had this invariant. WinEHPrepare did it for C++, but not SEH. The result was that we would insert calls to llvm.x86.seh.restoreframe in normal basic blocks, which corrupted the frame pointer. llvm-svn: 241699
* MC: Constify MCSubtargetInfo in getDeprecationInfo(), NFCDuncan P. N. Exon Smith2015-07-081-4/+4
| | | | | | | There's no reason to be able to mutate `MCSubtargetInfo` in `getDeprecationInfo()`. Constify the reference. llvm-svn: 241693
* Cosmetic cleanups - NFCEli Bendersky2015-07-082-6/+3
| | | | | | Remove commented lines, trailing whitespace, etc. llvm-svn: 241687
* [SPARC] Cleanup handling of the Y/ASR registers.James Y Knight2015-07-084-13/+22
| | | | | | | | | | | | | | | | | | - Implement copying ASR to/from GPR regs. - Mark ASRs as non-allocatable, so it won't try to arbitrarily use them inappropriately. - Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV routines, just do normal register copies. - Also...mark div as using Y, not just writing it. Added a test case with some code which previously died with an assertion failure (with -O0), or produced wrong code (otherwise). (Third time's the charm?) Differential Revision: http://reviews.llvm.org/D10401 llvm-svn: 241686
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-083-1/+1604
| | | | llvm-svn: 241683
* Revert 241681: causes Windows builds to failKrzysztof Parzyszek2015-07-083-1604/+1
| | | | llvm-svn: 241682
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-083-1/+1604
| | | | llvm-svn: 241681
* [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding supportSimon Pilgrim2015-07-081-4/+8
| | | | llvm-svn: 241671
* Remove IsLittleEndian from TargetLowering and redirect to DataLayoutMehdi Amini2015-07-082-10/+12
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11017 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241655
* [WinEH] Make llvm.x86.seh.restoreframe work for stack realignment prologuesReid Kleckner2015-07-075-32/+93
| | | | | | | | | | The incoming EBP value points to the end of a local stack allocation, so we can use that to restore ESI, the base pointer. Once we do that, we can use local stack allocations. If we know we need stack realignment, spill the original frame pointer in the prologue and reload it after restoring ESI. llvm-svn: 241648
* [WinEH] Add localaddress intrinsic instead of using frameaddressReid Kleckner2015-07-071-0/+13
| | | | | | | Clang uses this for SEH finally. The new intrinsic will produce the right value when stack realignment is required. llvm-svn: 241643
* Add more nvcastsArnold Schwaighofer2015-07-071-0/+8
| | | | | | | | | Tim Northover has told me that they can occur when the compiler cleverly constructs constants - as demonstrated in the test case. rdar://21703486 llvm-svn: 241641
* [WebAssembly] Set the scheduling preference.Dan Gohman2015-07-071-0/+2
| | | | llvm-svn: 241637
* Rename llvm.frameescape and llvm.framerecover to localescape and localrecoverReid Kleckner2015-07-075-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Initially, these intrinsics seemed like part of a family of "frame" related intrinsics, but now I think that's more confusing than helpful. Initially, the LangRef specified that this would create a new kind of allocation that would be allocated at a fixed offset from the frame pointer (EBP/RBP). We ended up dropping that design, and leaving the stack frame layout alone. These intrinsics are really about sharing local stack allocations, not frame pointers. I intend to go further and add an `llvm.localaddress()` intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being used to address locals, which should not be confused with the frame pointer. Naming suggestions at this point are welcome, I'm happy to re-run sed. Reviewers: majnemer, nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11011 llvm-svn: 241633
* fix typo; NFCSanjay Patel2015-07-071-1/+1
| | | | llvm-svn: 241629
* Add a pattern for a nvcast from v2f64 -> v4f32Arnold Schwaighofer2015-07-071-0/+1
| | | | | | | | | Since the NvCast is generated by the selection process the concerns about endianess and bit reversal don't apply. rdar://21703486 llvm-svn: 241611
* Use default member initializers to deduplicate code in ↵Reid Kleckner2015-07-071-50/+19
| | | | | | X86MachineFunctionInfo, NFC llvm-svn: 241609
* [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595Krzysztof Parzyszek2015-07-072-12/+8
| | | | llvm-svn: 241600
* [WinEH] Add a report_fatal_error for 32-bit stack realignmentReid Kleckner2015-07-071-0/+5
| | | | | | | | | This type of prologue isn't supported yet. Implementing it should be a matter of copying the adjusted incoming EBP into ESI (the base pointer) instead of EBP. The original EBP can be saved and restored from other memory afterwards. llvm-svn: 241597
* [Hexagon] Implement bit-tracking facility with specifics for HexagonKrzysztof Parzyszek2015-07-075-0/+2832
| | | | | | | | This includes code that is intended to be target-independent as well as the Hexagon-specific details. This is just the framework without any users. llvm-svn: 241595
* use range-based for loops; NFCISanjay Patel2015-07-071-35/+17
| | | | llvm-svn: 241592
* Fix gcc warnings of different enum and non-enum types in ternariesDenis Protivensky2015-07-072-9/+9
| | | | llvm-svn: 241567
* [ARM] Define a subtarget feature and use it to decide whether long calls shouldAkira Hatanaka2015-07-075-12/+14
| | | | | | | | | | | | | | | | | be emitted. This is needed to enable ARM long calls for LTO and enable and disable it on a per-function basis. Out-of-tree projects currently using EnableARMLongCalls to emit long calls should start passing "+long-calls" to the feature string (see the changes made to clang in r241565). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D9364 llvm-svn: 241566
* [X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with ↵Simon Pilgrim2015-07-062-5/+8
| | | | | | | | | | | | zero'd lanes The vperm2f128/vperm2i128 shuffle mask decoding was not attempting to deal with shuffles that give zero lanes. This patch fixes this so that the assembly printer can provide shuffle comments. As this decoder is also used in X86ISelLowering for shuffle combining, I've added an early-out to match existing behaviour. The hope is that we can add zero support in the future, this would allow other ops' decodes (e.g. insertps) to be combined as well. Differential Revision: http://reviews.llvm.org/D10593 llvm-svn: 241516
* [x86] extend machine combiner reassociation optimization to SSE scalar addsSanjay Patel2015-07-061-13/+19
| | | | | | | | | | | | Extend the reassociation optimization of http://reviews.llvm.org/rL240361 (D10460) to SSE scalar FP SP adds in addition to AVX scalar FP SP adds. With the 'switch' in place, we can trivially add other opcodes and test cases in future patches. Differential Revision: http://reviews.llvm.org/D10975 llvm-svn: 241515
* [X86][SSE] Vectorized i64 uniform constant SRA shiftsSimon Pilgrim2015-07-062-2/+51
| | | | | | | | This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-068-6/+300
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 ↵Simon Pilgrim2015-07-066-138/+177
| | | | | | | | | | | | implementation With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations. This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code. Differential Revision: http://reviews.llvm.org/D10947 llvm-svn: 241506
* llc: Add a 'run-pass' option.Alex Lorenz2015-07-062-3/+4
| | | | | | | | | | | | | | | This commit adds a 'run-pass' option to llc, which instructs the compiler to run one specific code generation pass only. Llc already has the 'start-after' and the 'stop-after' options, and this new option complements the other two by making it easier to write tests that want to invoke a single pass only. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10776 llvm-svn: 241476
* AMDGPU: Run SIInsertWaits as pre-emit passMatt Arsenault2015-07-061-1/+1
| | | | | | | | | | | Running this after the scheduler enables scheduling waits later so other ALU instructions can run while this would be waiting. When combined with enabling the post-RA scheduler, this gives about a ~20% improvement on sgemm. llvm-svn: 241473
* Change the last few internal StringRef triples into Triple objects.Daniel Sanders2015-07-0614-58/+59
| | | | | | | | | | | | | | | | | | | | Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
* Where Triple has a suitable predicate, use it rather than the enum values. NFC.Daniel Sanders2015-07-065-9/+7
| | | | | | | | | | Reviewers: mcrosier Subscribers: llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10960 llvm-svn: 241469
* AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault2015-07-064-1/+18
| | | | | | | | We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. llvm-svn: 241462
* [Sparc] Add more instruction aliases.James Y Knight2015-07-062-12/+125
| | | | | | | | | These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
* [Sparc] Add support for flush instruction.James Y Knight2015-07-062-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D9833 llvm-svn: 241460
* Fix a bug in the A57FPLoadBalancing register tracking/scavenger.Chad Rosier2015-07-061-3/+11
| | | | | | | | | | | | The code in AArch64A57FPLoadBalancing::scavengeRegister() to handle dead defs was not correctly handling aliased registers. E.g. if the dead def was of D2, then S2 was not being marked as unavailable, so it could potentially be used across a live-range in which it would be clobbered. Patch by Geoff Berry <gberry@codeaurora.org>! Phabricator: http://reviews.llvm.org/D10900 llvm-svn: 241449
* [X86][AVX512] Multiply Packed Unsigned Integers with Round and ScaleAsaf Badouh2015-07-065-0/+9
| | | | | | | | | pmulhrsw review: http://reviews.llvm.org/D10948 llvm-svn: 241443
* IR: Do not consider available_externally linkage to be linker-weak.Peter Collingbourne2015-07-0510-49/+32
| | | | | | | | | | | | | | | From the linker's perspective, an available_externally global is equivalent to an external declaration (per isDeclarationForLinker()), so it is incorrect to consider it to be a weak definition. Also clean up some logic in the dead argument elimination pass and clarify its comments to better explain how its behavior depends on linkage, introduce GlobalValue::isStrongDefinitionForLinker() and start using it throughout the optimizers and backend. Differential Revision: http://reviews.llvm.org/D10941 llvm-svn: 241413
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-0524-103/+75
| | | | | | | | There is some functional change here because it changes target code from atoi(3) to StringRef::getAsInteger which has error checking. For valid constraints there should be no difference. llvm-svn: 241411
* [x86][AVX512] add Multiply High OpAsaf Badouh2015-07-053-0/+12
| | | | | | | | | include encoding and intrinsics tests. review http://reviews.llvm.org/D10896 llvm-svn: 241406
* [X86] Fix incorrect/inefficient pushw encodings for x86-64 targetsMichael Kuperstein2015-07-052-9/+4
| | | | | | | | | | | | | Correctly support assembling "pushw $imm8" on x86-64 targets. Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually represent the same instruction) This fixes PR23996 Patch by: david.l.kreitzer@intel.com Differential Revision: http://reviews.llvm.org/D10878 llvm-svn: 241404
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