summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [Mips] TargetStreamer Support for .abicalls and .set pic0.Jack Carter2014-01-065-10/+77
| | | | | | | | | | This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. llvm-svn: 198646
* Remove dead code.Rafael Espindola2014-01-061-8/+0
| | | | llvm-svn: 198624
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-0619-60/+67
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* XCore Target: correct callee save register spilling when callsUnwindInit is ↵Robert Lytton2014-01-062-2/+20
| | | | | | true. llvm-svn: 198616
* XCore target: Lower EH_RETURNRobert Lytton2014-01-064-0/+66
| | | | llvm-svn: 198615
* XCore target: Lower FRAME_TO_ARGS_OFFSETRobert Lytton2014-01-067-0/+102
| | | | | | | | | This requires a knowledge of the stack size which is not known until the frame is complete, hence the need for the XCoreFTAOElim pass which lowers the XCoreISD::FRAME_TO_ARGS_OFFSET instrution into its final form. llvm-svn: 198614
* XCore target: Lower RETURNADDRRobert Lytton2014-01-062-2/+26
| | | | | | Only handles a depth of zero (the same as FRAMEADDR) llvm-svn: 198613
* XCore target: Optimise entsp / retsp selectionRobert Lytton2014-01-061-1/+9
| | | | llvm-svn: 198612
* XCore target: Refactor LR handlingRobert Lytton2014-01-063-48/+72
| | | | | | | | | We also narrow the liveness of FP & LR during the prologue to reflect the actual usage of the registers. I have been unable to construct a test to prove the previous live range was too large. llvm-svn: 198611
* XCore target: Refactor the loading of constants into a registerRobert Lytton2014-01-063-32/+49
| | | | | | This common functionality will be used to lower FRAME_TO_ARGS_OFFSET. llvm-svn: 198610
* XCore target: fix handling of unsized global arrays in large code modelRobert Lytton2014-01-061-4/+13
| | | | llvm-svn: 198609
* ARM: keep special non-AEABIness of "-darwin-eabi" triples for nowTim Northover2014-01-061-2/+5
| | | | | | | | | | Longer term, we want to move users to "*-*-*-macho" for embedded work, but for now people are relying on the last thing we told them, which is unfortunately "*-*-darwin-eabi". rdar://problem/15703934 llvm-svn: 198602
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-062-0/+9
| | | | llvm-svn: 198593
* [Sparc] Explicitly cast -1 to unsigned to fix buildbot errors.Venkatraman Govindaraju2014-01-061-8/+8
| | | | llvm-svn: 198592
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-0610-61/+371
| | | | llvm-svn: 198591
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-064-77/+46
| | | | llvm-svn: 198588
* Remove argument to fix build bot failure.Craig Topper2014-01-061-1/+1
| | | | llvm-svn: 198587
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-063-31/+35
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* Remove unnecessary #includes.Bill Wendling2014-01-068-8/+0
| | | | llvm-svn: 198585
* [x86] Add basic support for .code16Craig Topper2014-01-067-17/+79
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* [Sparc] Add ELF Object Writer for Sparc. Venkatraman Govindaraju2014-01-068-12/+287
| | | | llvm-svn: 198580
* Refactor function that checks that __builtin_returnaddress's argument is ↵Bill Wendling2014-01-068-32/+8
| | | | | | | | | constant. This moves the check up into the parent class so that all targets can use it without having to copy (and keep in sync) the same error message. llvm-svn: 198579
* ARM: move ARMUnwindOp.h into SupportSaleem Abdulrasool2014-01-064-154/+31
| | | | | | | | | Move the ARM EHABI unwind opcode definitions from the ARM MCTargetDesc into LLVM Support. This enables sharing of the definitions across the ARM target code as well as llvm-readobj. This will allow implementation of the unwind decoding in llvm-readobj. llvm-svn: 198576
* SPARC: Make helper function static.Benjamin Kramer2014-01-051-2/+2
| | | | llvm-svn: 198567
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-051-0/+60
| | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
* Remove opcode from MOV32r0 that I accidentally left when I converted it to ↵Craig Topper2014-01-051-2/+1
| | | | | | Pseudo. Remove FIXME as well. llvm-svn: 198564
* ARM: style changes to LDRD, STRD definitionSaleem Abdulrasool2014-01-051-11/+9
| | | | | | | | Fix indentation, name registers similar to ARM ARM. No functionality change! llvm-svn: 198563
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-052-24/+27
| | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. llvm-svn: 198562
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-053-37/+46
| | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. llvm-svn: 198557
* Add the other form of movq xmm,xmm for the disassembler.Craig Topper2014-01-051-0/+9
| | | | llvm-svn: 198551
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-051-8/+6
| | | | llvm-svn: 198550
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+4
| | | | llvm-svn: 198547
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-052-5/+5
| | | | | | disassembler without string matches. llvm-svn: 198545
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-051-2/+3
| | | | | | and remove disassmbler table emitter hack. llvm-svn: 198544
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-056-10/+20
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* [Sparc] Add initial implementation of MC Code emitter for sparc.Venkatraman Govindaraju2014-01-0510-4/+325
| | | | llvm-svn: 198533
* Emit an error message if the value passed to __builtin_returnaddress isn't a ↵Bill Wendling2014-01-058-0/+55
| | | | | | | | | | constant __builtin_returnaddress requires that the value passed into is be a constant. However, at -O0 even a constant expression may not be converted to a constant. Emit an error message intead of crashing. llvm-svn: 198531
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-051-18/+18
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-041-10/+18
| | | | | | Remove disassembler hack. llvm-svn: 198515
* [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju2014-01-0411-6/+689
| | | | llvm-svn: 198484
* [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. Venkatraman Govindaraju2014-01-041-39/+54
| | | | | | Fixes PR18356. llvm-svn: 198480
* Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it ↵Craig Topper2014-01-041-5/+0
| | | | | | won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. llvm-svn: 198475
* Make the llvm mangler depend only on DataLayout.Rafael Espindola2014-01-0322-50/+66
| | | | | | | | | | | | | | Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. llvm-svn: 198438
* [AArch64][NEON] Added SXTL and SXTL2 instruction aliasesAna Pazos2014-01-031-0/+17
| | | | llvm-svn: 198437
* [PPC] Fix comment to match function nameHal Finkel2014-01-021-1/+1
| | | | llvm-svn: 198362
* [PPC] Fix the scheduling of CR logicals on the P7Hal Finkel2014-01-022-2/+3
| | | | | | | | | | | CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each dispatch group. The old itinerary entry was just wrong (but has not mattered because we don't generate these instructions). This will matter when, in an upcoming commit, we start generating these instructions. llvm-svn: 198359
* [PPC] Use the correct immediate operands on 64-bit instructionsHal Finkel2014-01-022-12/+12
| | | | | | | | | | | Several of the 64-bit fixed-point instructions with immediate operands were using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64) operand definitions (u16imm instead of u16imm64, for example). This error has had no effect so far, but would have caused type-checking violations with an upcoming change. llvm-svn: 198356
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+2
| | | | llvm-svn: 198336
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+4
| | | | | | from the disassembler table builder. llvm-svn: 198327
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-023-145/+196
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
OpenPOWER on IntegriCloud