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* Allow misaligned stores in x86 fast-isel.Derek Schuff2013-04-181-5/+0
| | | | | | | | | | | | In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. llvm-svn: 179774
* [ms-inline asm] Simplify some logic and add a FIXME for unhandled unary minus.Chad Rosier2013-04-181-10/+13
| | | | llvm-svn: 179765
* Make this private method.Chad Rosier2013-04-181-4/+4
| | | | llvm-svn: 179764
* Fix for PR14824, An ARM Load/Store Optimization bugHao Liu2013-04-181-1/+17
| | | | llvm-svn: 179751
* [mips] Rename function.Akira Hatanaka2013-04-181-2/+2
| | | | llvm-svn: 179741
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-184-8/+99
| | | | llvm-svn: 179739
* Mips assembler: formatting and comment changes.Jack Carter2013-04-181-302/+294
| | | | | | This patch should not have any functional changes. llvm-svn: 179737
* Add support for subsections to the ELF assembler. Fixes PR8717.Peter Collingbourne2013-04-174-11/+14
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D598 llvm-svn: 179725
* [ms-inline asm] These should be int64_t, not uint64_t.Chad Rosier2013-04-171-6/+6
| | | | llvm-svn: 179724
* [ms-inline asm] Add support for the minus unary operator. Previously, we wereChad Rosier2013-04-171-72/+106
| | | | | | | | | | | unable to handle cases such as __asm mov eax, 8*-8. This patch also attempts to simplify the state machine. Further, the error reporting has been improved. Test cases included, but more will be added to the clang side shortly. rdar://13668445 llvm-svn: 179719
* This patch teaches x86 fast-isel to generate the native div/idiv instructionsEli Bendersky2013-04-171-0/+125
| | | | | | | | | for the sdiv/srem/udiv/urem bitcode instructions. This is done for the i8, i16, and i32 types, as well as i64 for the x86_64 target. Patch by Jim Stichnoth llvm-svn: 179715
* X86 cost model: Exit before calling getSimpleVT on non-simple VTsArnold Schwaighofer2013-04-171-0/+4
| | | | | | | | getSimpleVT can only handle simple value types. radar://13676022 llvm-svn: 179714
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-173-4/+29
| | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179707
* PowerPC: Mark some more patterns as isCodeGenOnly.Ulrich Weigand2013-04-172-0/+6
| | | | | | | | | | A couple of recently introduced conditional branch patterns also need to be marked as isCodeGenOnly since they cannot be handled by the asm parser. No change in generated code. llvm-svn: 179690
* R600: Make Export Instruction not duplicableVincent Lejeune2013-04-171-1/+3
| | | | llvm-svn: 179686
* R600: Export is emitted as a CF_NATIVE instVincent Lejeune2013-04-172-14/+9
| | | | llvm-svn: 179685
* R600: Emit used GPRs countVincent Lejeune2013-04-172-8/+41
| | | | llvm-svn: 179684
* Fix -Werror build.Evgeniy Stepanov2013-04-171-0/+2
| | | | | | Broken in r179657. llvm-svn: 179669
* Mips assembler: Enable handling of nested expressionsJack Carter2013-04-172-133/+237
| | | | | | | | | | This patch allows the Mips assembler to parse and emit nested expressions as instruction operands. It also extends the expansion of memory instructions when an offset is given as an expression. Contributer: Vladimir Medic llvm-svn: 179657
* [ms-inline asm] Add support for parsing complex immediate expressions. TestChad Rosier2013-04-171-32/+51
| | | | | | | cases to be submitted on clang side shortly. rdar://13663768 and PR15760 llvm-svn: 179655
* C API: Add LLVMTargetMachineEmitToMemoryBuffer()Tom Stellard2013-04-161-12/+33
| | | | llvm-svn: 179648
* Remove unused variable from previous refactor.Chad Rosier2013-04-161-3/+0
| | | | llvm-svn: 179611
* [ms-inline asm] Refactor. No functional change intended.Chad Rosier2013-04-161-405/+419
| | | | llvm-svn: 179610
* [ms-inline asm] Remove some dead code.Chad Rosier2013-04-161-8/+0
| | | | llvm-svn: 179607
* Fix build failure introduced in 179591 when assertions are disabled.Logan Chien2013-04-161-0/+4
| | | | llvm-svn: 179593
* Implement ARM unwind opcode assembler.Logan Chien2013-04-165-45/+427
| | | | llvm-svn: 179591
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-162-0/+42
| | | | llvm-svn: 179582
* ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach2013-04-152-0/+19
| | | | | | | | | These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 llvm-svn: 179575
* Mips assembler: Explicit floating point condition register recognition.Jack Carter2013-04-151-0/+3
| | | | | | | | | | This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-152-3/+38
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | llvm-svn: 179545
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | llvm-svn: 179544
* Mark all PPC comparison instructions as not having side effectsHal Finkel2013-04-152-20/+28
| | | | | | | | | | Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. llvm-svn: 179502
* Fix PPC64 CR spill location for callee-saved registersHal Finkel2013-04-152-35/+50
| | | | | | | | | | | | | | | | This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-144-7/+8
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-141-6/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen2013-04-141-16/+34
| | | | | | | 64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. llvm-svn: 179472
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-142-26/+36
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-4/+2
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-143-14/+95
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriatelyHal Finkel2013-04-133-15/+16
| | | | | | | | | | | | Leaving MFCR has having unmodeled side effects is not enough to prevent unwanted instruction reordering post-RA. We could probably apply a stronger barrier attribute, but there is a better way: Add all (not just the first) CR to be spilled as live-in to the entry block, and add all CRs to the MFCR instruction as implicitly killed. Unfortunately, I don't have a small test case. llvm-svn: 179465
* Define SPARC code models.Jakob Stoklund Olesen2013-04-132-4/+32
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen2013-04-131-3/+4
| | | | | | | It doesn't seem like anybody is checking types this late in isel, so no test case. llvm-svn: 179462
* Spill and restore PPC CR registers using the FP when we have oneHal Finkel2013-04-131-6/+14
| | | | | | | | | | For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). llvm-svn: 179457
* X86 machine model: reduce SandyBridge and Haswell ILPWindow.Andrew Trick2013-04-132-2/+2
| | | | | | | | | | | | | | | The initial values were arbitrary. I want them to be more conservative. This represents the number of latency cycles hidden by OOO execution. In practice, I think it should be within a small factor of the complex floating point operation latency so the scheduler can make some attempt to hide latency even for smallish blocks. These are by no means the best values, just a starting point for tuning heuristics. Some benchmarks such as TSVC run faster with this lower value for SandyBridge. I haven't run anything on Haswell, but it's shouldn't be 2x SB. llvm-svn: 179450
* Catch another case where SD fails to propagate node order.Andrew Trick2013-04-131-1/+4
| | | | | | | | | | I need to handle this for the test case in my following scheduler commit. Work is already under way to redesign the mechanism for node order propagation because this case by case approach is unmaintainable. llvm-svn: 179448
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-134-172/+174
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-134-11/+41
| | | | llvm-svn: 179434
* [mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179433
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