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* Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel to ↵Renato Golin2015-01-301-7/+7
| | | | | | | | respect the debug location of comparisons in jumps." This reverts commit r227488 as it was failing ARM bots. llvm-svn: 227600
* [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.Colin LeMahieu2015-01-303-8/+213
| | | | llvm-svn: 227598
* ARM: improve caret diagnostics for invalid FPU nameSaleem Abdulrasool2015-01-301-1/+2
| | | | | | | In the case of an invalid FPU name, place the caret at the name rather than FPU directive. llvm-svn: 227595
* [Hexagon] Adding a number of vector load variants and organizing tests.Colin LeMahieu2015-01-302-16/+92
| | | | llvm-svn: 227588
* ARM: correct handling of .fpu directiveSaleem Abdulrasool2015-01-301-23/+35
| | | | | | | | | | | | | The FPU directive permits the user to switch the target FPU, enabling instructions that would be otherwise unavailable. However, when configuring the new subtarget features, we would not enable the implied functions for newer FPUs. This would result in invalid rejection of valid input. Ensure that we inherit the implied FPU functionality when enabling newer versions of the FPU. Fortunately, these are mostly hierarchical, unlike the CPUs. Addresses PR22395. llvm-svn: 227584
* tidy up; NFCSanjay Patel2015-01-301-6/+5
| | | | llvm-svn: 227582
* [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, ↵Toma Tabacu2015-01-302-2/+55
| | | | | | | | | | | | | | | | | | | | | | | | | instead of using InstAlias. Summary: This is needed by the .cprestore assembler directive. This directive needs to be able to insert an LW instruction after every JALR replacement of a JAL pseudo-instruction (and never after a JALR which has NOT been a result of a pseudo-instruction replacement). The problem with using InstAlias for these is that after it replaces the pseudo-instruction, we can't find out if the resulting JALR instruction was generated by an InstAlias or not, so we don't know whether or not to insert our LW instruction. By replacing it manually, we know when the pseudo-instruction replacement happens and we can insert the LW instruction correctly. Reviewers: dsanders Reviewed By: dsanders Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D5601 llvm-svn: 227568
* [AArch64]Fix PR21675, a bug about lowering llvm.ctpop.i32. We should noot ↵Hao Liu2015-01-301-10/+4
| | | | | | | | use "DAG.getUNDEF(MVT::v8i8)" to get all zero vector. Patch by Wei-cheng Wang. llvm-svn: 227550
* Use the cached subtarget in PPCFrameLowering.Eric Christopher2015-01-301-13/+12
| | | | llvm-svn: 227548
* Migrate some of PPC away from the use of bare getSubtarget/getSubtargetImpl.Eric Christopher2015-01-302-10/+10
| | | | llvm-svn: 227547
* Migrage PPCRegisterInfo to use the cached subtarget.Eric Christopher2015-01-301-29/+22
| | | | llvm-svn: 227546
* Migrate a bare getSubtarget call to query the MachineFunctionEric Christopher2015-01-301-3/+3
| | | | | | for the target dependent one. llvm-svn: 227542
* Migrate NVPTXISelLowering to take the subtarget that it's dependentEric Christopher2015-01-303-18/+19
| | | | | | upon as an argument and store/use that in the entire function. llvm-svn: 227541
* Remove unused argument.Eric Christopher2015-01-301-6/+5
| | | | llvm-svn: 227539
* Migrate NVPTXISelDAGToDAG's getSubtarget to a runOnMachineFunctionEric Christopher2015-01-303-52/+56
| | | | | | version. Update NVPTXInstrInfo accordingly. llvm-svn: 227538
* Remove calls to bare getSubtarget and clean up the functionsEric Christopher2015-01-302-11/+9
| | | | | | accordingly. llvm-svn: 227535
* Remove a few getSubtarget calls in AArch64 pass manager initialization.Eric Christopher2015-01-301-2/+2
| | | | llvm-svn: 227531
* Clean up some uses of getSubtarget in AArch64.Eric Christopher2015-01-306-23/+12
| | | | llvm-svn: 227530
* This only needs TargetInstrInfo, not the specialized one.Eric Christopher2015-01-301-3/+3
| | | | llvm-svn: 227529
* x86: Remove unused variables not caught by MSVC =PReid Kleckner2015-01-302-3/+0
| | | | llvm-svn: 227520
* x86: Fix large model calls to __chkstk for dynamic allocasReid Kleckner2015-01-293-84/+64
| | | | | | | | | | | | In the large code model, we now put __chkstk in %r11 before calling it. Refactor the code so that we only do this once. Simplify things by using __chkstk_ms instead of __chkstk on cygming. We already use that symbol in the prolog emission, and it simplifies our logic. Second half of PR18582. llvm-svn: 227519
* Remove unnecessary calls to getSubtarget/getSubtargetImpl from theEric Christopher2015-01-292-10/+3
| | | | | | MSP430 backend. llvm-svn: 227517
* Remove unused header.Eric Christopher2015-01-291-1/+0
| | | | llvm-svn: 227516
* Change SmallVector param to the more general ArrayRef; NFCISanjay Patel2015-01-291-1/+1
| | | | llvm-svn: 227514
* Get rid of a few calls through the subtarget to get the ABIEric Christopher2015-01-293-15/+15
| | | | | | that's actually sitting on the target machine. llvm-svn: 227513
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-2920-309/+196
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* x86: Remove the W64ALLOCA pseudoReid Kleckner2015-01-293-15/+3
| | | | | | | | | This is just an alias for CALL64pcrel32, and we can just use that opcode with explicit defs in the MI. No functionality change. llvm-svn: 227508
* [AArch64] Add INITIALIZE_PASS macros to AArch64A57FPLoadBalancing.Chad Rosier2015-01-291-1/+15
| | | | | | | | | | These are needed so this pass will produce output when e.g. -print-after-all is used. Phabricator Review: http://reviews.llvm.org/D7264 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227506
* Update comments to use unreachable instead of llvm.trap, as implemented nowReid Kleckner2015-01-293-12/+30
| | | | | | | | | | | | | win64: Call __chkstk through a register with the large code model Fixes half of PR18582. True dynamic allocas will still have a CALL64pcrel32 which will fail. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D7267 llvm-svn: 227503
* [Hexagon] Organizing tests and adding a few missing jump instruction encodings.Colin LeMahieu2015-01-292-1/+33
| | | | llvm-svn: 227498
* [Hexagon] Adding missing instruction encodings and tests.Colin LeMahieu2015-01-292-37/+24
| | | | llvm-svn: 227495
* [Hexagon] Adding alu vector instructionsColin LeMahieu2015-01-292-3/+177
| | | | llvm-svn: 227493
* Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the ↵David Blaikie2015-01-291-7/+7
| | | | | | debug location of comparisons in jumps. llvm-svn: 227488
* R600/SI: Implement enableAggressiveFMAFusionMatt Arsenault2015-01-292-1/+31
| | | | | | | | | Add tests for the various combines. This should always be at least cycle neutral on all subtargets for f64, and faster on some. For f32 we should prefer selecting v_mad_f32 over v_fma_f32. llvm-svn: 227484
* R600/SI: Add subtarget feature for if f32 fma is fastMatt Arsenault2015-01-295-5/+23
| | | | llvm-svn: 227483
* R600/SI: Fix tonga's basic scheduling modelMatt Arsenault2015-01-291-1/+1
| | | | llvm-svn: 227482
* DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumpsDavid Blaikie2015-01-291-9/+9
| | | | | | | | | The use of the DbgLoc in FastISel is probably something we should fix. It's prone to leaking the wrong location into instructions - we should have a clear chain of custody from the debug location of an IR Instruction to that of a MachineInstr to avoid such leakage. llvm-svn: 227481
* Compute the ELF SectionKind from the flags.Rafael Espindola2015-01-2910-133/+82
| | | | | | | | | | | | Any code creating an MCSectionELF knows ELF and already provides the flags. SectionKind is an abstraction used by common code that uses a plain MCSection. Use the flags to compute the SectionKind. This removes a lot of guessing and boilerplate from the MCSectionELF construction. llvm-svn: 227476
* [Hexagon] Deleting old variants of intrinsics and adding missing tests.Colin LeMahieu2015-01-293-186/+60
| | | | llvm-svn: 227474
* [Hexagon] Adding CR intrinsic tests.Colin LeMahieu2015-01-291-0/+26
| | | | llvm-svn: 227463
* R600/SI: Remove stray debug statementsTom Stellard2015-01-291-5/+1
| | | | llvm-svn: 227462
* R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard2015-01-294-6/+94
| | | | | | The schedule model is not complete yet, and could be improved. llvm-svn: 227461
* [Hexagon] Deleting unused classes.Colin LeMahieu2015-01-291-1319/+0
| | | | llvm-svn: 227460
* [X86] Use single add/sub for large stack offsetsRobert Lougher2015-01-291-13/+46
| | | | | | | | | | | For large stack offsets the compiler generates multiple immediate mode sub/add instructions in the prologue/epilogue. This patch makes the compiler place the final amount to be added/subtracted into a register, which is then added/substracted with a single operation. Differential Revision: http://reviews.llvm.org/D7226 llvm-svn: 227458
* [Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to ↵Colin LeMahieu2015-01-293-0/+30
| | | | | | i32 instead of i1. llvm-svn: 227457
* [PowerPC] Complete setting the baseline for ppc64leBill Schmidt2015-01-291-2/+7
| | | | | | | | | | | | Patch by Nemanja Ivanovic. As was uncovered by the failing test case (when run on non-PPC platforms), the feature set when compiling with -march=ppc64le was not being picked up. This change ensures that if the -mcpu option is not specified, the correct feature set is picked up regardless of whether we are on PPC or not. llvm-svn: 227455
* Remove MergeableConst.Rafael Espindola2015-01-291-1/+2
| | | | | | | Only the specific ones (MergeableConst4, MergeableConst8, MergeableConst16) are handled specially. llvm-svn: 227440
* [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 ↵Vladimir Medic2015-01-292-0/+23
| | | | | | it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
* Remove getSubtargetImpl from AArch64ISelLowering and cache theEric Christopher2015-01-293-13/+10
| | | | | | | correct subtarget by passing it in during the constructor as TargetLowering is Subtarget specific. llvm-svn: 227402
* Remove getSubtargetImpl from ARMISelLowering and cache theEric Christopher2015-01-293-33/+22
| | | | | | | correct subtarget by passing it in during the constructor as TargetLowering is Subtarget specific. llvm-svn: 227401
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