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* Large stack frame patch for the CellSPU: handle stack frames that exceed 8176Scott Michel2010-02-253-11/+150
| | | | | | | | | | | | | (511*16) bytes register displacement (D-form). NOTE: This is a potential headache, given the SPU's local core limitations, allowing the software developer to commit stack overrun suicide unknowingly. Also, large SPU stack frames will cause code size explosion. But, one presumes that the software developer knows what they're doing... Contributed by Kalle.Raiskila@nokia.com, edited slightly before commit. llvm-svn: 97091
* Create a stack frame on ARM whenJakob Stoklund Olesen2010-02-241-41/+41
| | | | | | | | | | | - Function uses all scratch registers AND - Function does not use any callee saved registers AND - Stack size is too big to address with immediate offsets. In this case a register must be scavenged to calculate the address of a stack object, and the scavenger needs a spare register or emergency spill slot. llvm-svn: 97071
* Check for comparisons of +/- zero when optimizing less-than-or-equal andBob Wilson2010-02-241-22/+31
| | | | | | | | greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is only allowed when UnsafeFPMath is set or when at least one of the operands is known to be nonzero. llvm-svn: 97065
* Make getTypeSizeInBits work correctly for array types; it should returnDan Gohman2010-02-241-1/+42
| | | | | | | | | | | | | | | the number of value bits, not the number of bits of allocation for in-memory storage. Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and vectors. Fix several places in CodeGen which compute offsets into in-memory vectors to use TargetData information. This fixes PR1784. llvm-svn: 97064
* Adding function "lookupGCCName" to MBlazeIntrinsicInfoWesley Peck2010-02-245-13/+17
| | | | | | | | | | | Adding the function "lookupGCCName" to the MBlazeIntrinsicInfo class to support the Clang MicroBlaze target. Additionally, minor fixes which remove some unused PIC code (PIC is not supported yet in the MicroBlaze backend) and removed some unused variables. llvm-svn: 97054
* Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.Johnny Chen2010-02-241-0/+8
| | | | | | A8.6.405 llvm-svn: 97052
* Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understandJakob Stoklund Olesen2010-02-241-1/+9
| | | | | | | <undef> operands, and can cause scavenger failures when it translates <kill,undef> to <kill>. llvm-svn: 97046
* Fixed typo of opcodestr, should be "vst1", not "vld1".Johnny Chen2010-02-241-9/+9
| | | | llvm-svn: 97044
* Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again inDaniel Dunbar2010-02-241-36/+16
| | | | | | the hopes of fixing PPC bootstrap. llvm-svn: 97040
* When forming SSE min and max nodes for UGE and ULE comparisons, it'sDan Gohman2010-02-241-10/+74
| | | | | | | | | | | necessary to swap the operands to handle NaN and negative zero properly. Also, reintroduce logic for checking for NaN conditions when forming SSE min and max instructions, fixed to take into consideration NaNs and negative zeros. This allows forming min and max instructions in more cases. llvm-svn: 97025
* Remove an unused variable. Was this intentional?Chandler Carruth2010-02-241-1/+0
| | | | llvm-svn: 97022
* Added for disassembly VST1 (multiple single elements) which stores elements toJohnny Chen2010-02-241-0/+35
| | | | | | | | | memory from three or four registers and VST2 (multiple two-element structures) which stores to memory from two double-spaced registers. A8.6.391 & A8.6.393 llvm-svn: 97018
* handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach2010-02-242-4/+4
| | | | llvm-svn: 97013
* LowerCall() should always do getCopyFromReg() to reference the stack pointer.Jim Grosbach2010-02-241-5/+1
| | | | | | | Machine instruction selection is much happier when operands are in virtual registers. llvm-svn: 97012
* Re-apply 96540 and 96556 with fixes.Evan Cheng2010-02-241-16/+36
| | | | llvm-svn: 97011
* DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses itJakob Stoklund Olesen2010-02-241-1/+1
| | | | | | instead of %AL/%AH. llvm-svn: 97006
* Fix rev 96389 by restricting the xform to mask that's either signbit or max ↵Evan Cheng2010-02-231-4/+9
| | | | | | signed value. llvm-svn: 96990
* Don't mark call instruction as a barrier.Richard Osborne2010-02-231-1/+1
| | | | llvm-svn: 96983
* Added for disassembly VLD1 (multiple single elements) which loads memory intoJohnny Chen2010-02-231-0/+33
| | | | | | | | | three or four registers and VLD2 (multiple two-element structures) which loads memory into two double-spaced registers. A8.6.307 & A8.6.310 llvm-svn: 96980
* Use the module's context instead of the global context.Nicolas Geoffray2010-02-231-16/+16
| | | | llvm-svn: 96977
* no need to override IsLegalToFold, the base implementationChris Lattner2010-02-231-10/+0
| | | | | | disables load folding at -O0. llvm-svn: 96973
* Adding the MicroBlaze backend.Wesley Peck2010-02-2337-0/+5371
| | | | | | | | | | | | The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
* ECALLF, ECALLT shouldn't be marked as barriers.Richard Osborne2010-02-231-2/+2
| | | | llvm-svn: 96964
* Mark unconditional branches as barriers. Found using -verify-machineinstrsRichard Osborne2010-02-231-3/+3
| | | | llvm-svn: 96960
* Spelling. s/suppor /support /Jim Grosbach2010-02-231-3/+3
| | | | llvm-svn: 96954
* Remove unused lowering function LowerJumpTableRichard Osborne2010-02-232-13/+0
| | | | llvm-svn: 96943
* Lower BR_JT on the XCore to a jump into a series of jump instructions.Richard Osborne2010-02-235-5/+103
| | | | llvm-svn: 96942
* disable two patterns that are using non-sensical result pattern types.Chris Lattner2010-02-231-4/+4
| | | | llvm-svn: 96903
* remove a confused pattern that is trying to match an addressChris Lattner2010-02-231-7/+0
| | | | | | then use it as an MMX register (!?). llvm-svn: 96901
* remove a bunch of dead named arguments in input patterns,Chris Lattner2010-02-235-46/+46
| | | | | | though some look dubious afaict, these are all ok. llvm-svn: 96899
* fix a type mismatch in this pattern, where we were using an i64 imm in a Chris Lattner2010-02-231-1/+7
| | | | | | | | place where an i32 imm was required, the old isel just got lucky. This fixes CodeGen/X86/x86-64-and-mask.ll llvm-svn: 96894
* reapply my cellspu changes with a fix to not break the old isel.Chris Lattner2010-02-231-42/+73
| | | | llvm-svn: 96885
* Revert 96854, 96852, and 96849, unbreaking test/CodeGen/CellSPU/i64ops.ll.Dan Gohman2010-02-231-71/+42
| | | | llvm-svn: 96871
* X86InstrInfoSSE.td declares PINSRW as having type v8i16,Chris Lattner2010-02-233-7/+19
| | | | | | | don't alis it in the MMX .td file with a different width, split into two X86ISD opcodes. This fixes an x86 testcase. llvm-svn: 96859
* Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare toJohnny Chen2010-02-231-9/+25
| | | | | | | | (immediate #0) for disassembly only. A8.6.283, A8.6.285, A8.6.287, A8.6.290 llvm-svn: 96856
* fix hte last cellspu failure.Chris Lattner2010-02-231-11/+12
| | | | llvm-svn: 96854
* hack around more crimes in instruction selection.Chris Lattner2010-02-231-16/+26
| | | | llvm-svn: 96852
* the cell backend is making all sorts of unsafe and incorrect assumptions Chris Lattner2010-02-231-26/+44
| | | | | | | about ownership and update policies. It isn't clear why it is doing all this lowering at isel time instead of in legalize. This fixes fcmp64.ll llvm-svn: 96849
* Added VCEQ (immediate #0) NEON instruction for disassembly only.Johnny Chen2010-02-231-0/+41
| | | | | | A8.6.281 llvm-svn: 96838
* Updated version of r96634 (which was reverted due to failing 176.gcc andJim Grosbach2010-02-224-2/+19
| | | | | | | | 126.gcc nightly tests. These failures uncovered latent bugs that machine DCE could remove one half of a stack adjust down/up pair, causing PEI to assert. This update fixes that, and the tests now pass. llvm-svn: 96822
* Clean up a bit and fix for when SPAdj != 0Jim Grosbach2010-02-221-3/+2
| | | | llvm-svn: 96818
* The predicate index isn't fixed, so scan for it to make sure we get the properJim Grosbach2010-02-221-2/+3
| | | | | | | | | value. Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so remove the FIXME entry. llvm-svn: 96817
* remove dupes now.Chris Lattner2010-02-221-2/+0
| | | | llvm-svn: 96811
* move #includes earlier.Chris Lattner2010-02-222-2/+3
| | | | llvm-svn: 96810
* Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,Johnny Chen2010-02-221-5/+83
| | | | | | for disassembly only. llvm-svn: 96806
* Added a bunch of instructions for disassembly only:Johnny Chen2010-02-221-19/+145
| | | | | | | | | | o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
* Mark the return address stack slot as mutable when moving the return addressArnold Schwaighofer2010-02-221-2/+2
| | | | | | | | | | | | | | | | | during a tail call. A parameter might overwrite this stack slot during the tail call. The sequence during a tail call is: 1.) load return address to temp reg 2.) move parameters (might involve storing to return address stack slot) 3.) store return address to new location from temp reg If the stack location is marked immutable CodeGen can colocate load (1) with the store (3). This fixes bug 6225. llvm-svn: 96783
* Fix a typo in a comment.Dan Gohman2010-02-221-1/+1
| | | | llvm-svn: 96778
* Remove the logic for reasoning about NaNs from the code that formsDan Gohman2010-02-221-88/+11
| | | | | | | | | | SSE min and max instructions. The real thing this code needs to be concerned about is negative zero. Update the sse-minmax.ll test accordingly, and add tests for -enable-unsafe-fp-math mode as well. llvm-svn: 96775
* fix an incorrect VT: eflags is always i32. The bug was causing us toChris Lattner2010-02-221-1/+1
| | | | | | | | create an X86ISD::Cmp node with result type i64 on the CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it downstream. llvm-svn: 96768
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